Kentaroh Katoh

According to our database, Kentaroh Katoh authored at least 21 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing.

Shogo Katayama, Takayuki Nakatani, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi

IEICE Electron. Express, 2023

Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion.

Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Shuhei Yamamoto, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi

Proceedings of the IEEE International Test Conference, 2023

A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation.

Kentaroh Katoh, Shuhei Yamamoto, Zheming Zhao, Yujie Zhao, Shogo Katayama, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa

Proceedings of the IEEE International Test Conference in Asia, 2023

2022

Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies.

Yujie Zhao, Kentaroh Katoh, Anna Kuwana, Shogo Katayama, Jianglin Wei, Haruo Kobayashi, Takayuki Nakatani, Kazumi Hatayama, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa

J. Electron. Test., 2022

Innovative Practices Track: Innovative Analog Circuit Testing Technologies.

Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOST.

Keno Sato, Takayuki Nakatani, Shogo Katayama, Daisuke Iimori, Gaku Ogihara, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Yujie Zhao, Kentaroh Katoh, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi

Proceedings of the IEEE 31st Asian Test Symposium, 2022

2015

Erratum to: A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator.

Kentaroh Katoh, Yutaro Kobayashi, Takeshi Chujo, Junshan Wang, Ensi Li, Congbing Li, Haruo Kobayashi

J. Electron. Test., 2015

A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement.

Kentaroh Katoh, Kazuteru Namba

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014

Analog/mixed-signal circuit design in nano CMOS era.

Haruo Kobayashi, Hitoshi Aoki, Kentaroh Katoh, Congbing Li

IEICE Electron. Express, 2014

A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator.

Kentaroh Katoh, Yutaro Kobayashi, Takeshi Chujo, Junshan Wang, Ensi Li, Congbing Li, Haruo Kobayashi

J. Electron. Test., 2014

2013

Digital Compensation for Timing Mismatches in Interleaved ADCs.

Ru Yi, Minghui Wu, Koji Asami, Haruo Kobayashi, Ramin Khatami, Atsuhiro Katayama, Isao Shimizu, Kentaroh Katoh

Proceedings of the 22nd Asian Test Symposium, 2013

An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators.

Kentaroh Katoh, Yuta Doi, Satoshi Ito, Haruo Kobayashi, Ensi Li, Nobukazu Takai

Proceedings of the 22nd Asian Test Symposium, 2013

2012

An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection.

Kentaroh Katoh, Kazuteru Namba, Hideo Ito

IEEE Trans. Very Large Scale Integr. Syst., 2012

2010

A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit.

Kentaroh Katoh, Kazuteru Namba, Hideo Ito

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths.

Kentaroh Katoh, Kazuteru Namba, Hideo Ito

IEICE Trans. Inf. Syst., 2009

Design for Delay Fault Testability of 2-Rail Logic Circuits.

Kentaroh Katoh, Kazuteru Namba, Hideo Ito

IEICE Trans. Inf. Syst., 2009

A Delay Measurement Technique Using Signature Registers.

Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability.

Kentaroh Katoh, Kazuteru Namba, Hideo Ito

IPSJ Trans. Syst. LSI Des. Methodol., 2008

2007

Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability.

Abderrahim Doumar, Kentaroh Katoh, Hideo Ito

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006

Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices.

Kentaroh Katoh, Hideo Ito

Proceedings of the 11th European Test Symposium, 2006

2005

Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift.

Kentaroh Katoh, Abderrahim Doumar, Hideo Ito

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005