Abdoul Rjoub

Orcid: 0000-0001-8948-8070

According to our database1, Abdoul Rjoub authored at least 28 papers between 1998 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Bibliography

2022
ICT Smart Water Management System for Real-Time Applications.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

2019
Nanotube Deflections: A comparative Assessment of the State-of-the-Art.
Proceedings of the 31st International Conference on Microelectronics, 2019

2018
Low Power High Speed MISTY1 Cryptography Approaches.
J. Circuits Syst. Comput., 2018

Modelling and simulation tools for nanoscale transistor sizing.
Int. J. Simul. Process. Model., 2018

2015
A fast input vector control approach for sub-threshold leakage current reduction at nanoscale transistors.
Int. J. Model. Identif. Control., 2015

2014
Gate leakage current accurate models for nanoscale MOSFET transistors.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Fast modeling technique for nano scale CMOS inverter and propagation delay estimation.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

2013
Accurate subthreshold leakage model for nanoscale MOSFET transistor.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
The performance and behaviour of dual edge triggered flip-flops in nanotechnology.
Int. J. Comput. Aided Eng. Technol., 2012

Estimating the starting point of conduction in nanoscale CMOS gates.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

High speed FPGA implementation of hough transform for real-time applications.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Efficient multi-threshold voltage techniques for minimum leakage current in nanoscale technology.
Int. J. Circuit Theory Appl., 2011

Pass Transistor Operation Modeling for Nanoscale Technologies.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

2010
The Influence of the Nanometer Technology on Performance of CPL Full Adders.
J. Comput., 2010

Full custom low-power/high performance DDP-based Cobra-H64 cipher.
Comput. Electr. Eng., 2010

Low leakage multi-Vth technique for sequential circuits at transistor level in nanotechnology.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2007
An optimal low-power/high performance DDP-based Cobra-H64 cipher.
Proceedings of the 3rd International Conference on Mobile Multimedia Communications, 2007

2004
An Efficient Low-Swing Multithreshold-Voltage Low-Power Design Technique.
J. Circuits Syst. Comput., 2004

Multithreshold voltage low-swing/low-voltage techniques in logic gates.
Integr., 2004

Low power high-speed multithreshold voltage CMOS bus architectures.
Comput. Electr. Eng., 2004

2001
Efficient Low Power/Low Swing Bus Design Architectures.
VLSI Design, 2001

Multi-level low swing voltage values for low power design applications.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Multiple low swing voltage values for CPL, CVSL and domino logic families.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1999
Low voltage swing gates for low power consumption.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Multithreshold Voltage Technology for Low Power Bus Architecture.
Proceedings of the VLSI: Systems on a Chip, 1999

Efficient drivers, receivers and repeaters for low power CMOS bus architectures.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Low-swing/low power driver architecture.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
Low-power domino logic multiplier using low-swing technique.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998


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