Spiridon Nikolaidis

Orcid: 0000-0002-9794-8062

Affiliations:
  • Aristotle University of Thessaloniki, Department of Physics, Greece


According to our database1, Spiridon Nikolaidis authored at least 135 papers between 1991 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Unconventional Security for IoT: Hardware and Software Implementation of a Digital Chaotic Encrypted Communication Scheme.
IEEE Internet Things J., June, 2024

Energy Consumption Aspects on Embedded System for IoT Applications.
Proceedings of the 13th International Conference on Modern Circuits and Systems Technologies, 2024

Performance Evaluation of Different Finite State Machines Implementations.
Proceedings of the 13th International Conference on Modern Circuits and Systems Technologies, 2024

Byzantine Hymn Recognition with Audio Fingerprints Resistant to Noise, Tempo and Scale Changes.
Proceedings of the 13th International Conference on Modern Circuits and Systems Technologies, 2024

Energy Harvesting & Autonomous Energy Systems: A Proposal for RF Energy Harvesting.
Proceedings of the 13th International Conference on Modern Circuits and Systems Technologies, 2024

2023
Music Deep Learning: Deep Learning Methods for Music Signal Processing - A Review of the State-of-the-Art.
IEEE Access, 2023

Recognition of Greek Orthodox Hymns Using Audio Fingerprint Techniques.
Proceedings of the 8th South-East Europe Design Automation, 2023

Exploration of Bistable Oscillatory Dynamics in a Memristor from Forschungszentrum Jülich.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023

The Challenges of Music Deep Learning for Traditional Music.
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023

2022
Acoustic Leak Localization Method for Pipelines in High-Noise Environment Using Time-Frequency Signal Segmentation.
IEEE Trans. Instrum. Meas., 2022

A Statistical Approach for Leak Monitoring of Highly Noisy Metallic Pipelines.
IEEE Trans. Instrum. Meas., 2022

Comparative Performance of Algorithmic Techniques for Optimizing Dual-Band Rectifier.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

Acoustic method for leak size estimation in fluid-carrying pipelines.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

Smart Refrigeration Equipment based on IoT Technology for Reducing Power Consumption.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

Music Deep Learning: A Survey on Deep Learning Methods for Music Processing.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

Rectifier circuit design for 5G energy harvesting applications.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

2021
Acoustic leak localization method based on signal segmentation and statistical analysis.
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021

Applying One Class Classification for Leak Detection in Noisy Industrial Pipelines.
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021

Dealing with stochastic signals and physical phenomena impacting pipeline leak localization accuracy.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2021

An RMS-based Approach for Leak Monitoring in Noisy Industrial Pipelines.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2021

2020
Dual-Band RF-to-DC Rectifier with High Efficiency for RF Energy Harvesting Applications.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

Applying the Power Contributors Method in a complex CMOS cell.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

Machine Learning Model Comparison for Leak Detection in Noisy Industrial Pipelines.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

Defining thresholds for leak detection parameters through statistical analysis of the noise in water/gas pipelines.
Proceedings of the 2020 IEEE International Instrumentation and Measurement Technology Conference, 2020

Fast leak localization based on acoustic signal attenuation for pipelines in high-noise environment.
Proceedings of the European Conference on Circuit Theory and Design, 2020

Dual-Band Single-Layered Modified E-shaped Patch Antenna for RF Energy Harvesting Systems.
Proceedings of the European Conference on Circuit Theory and Design, 2020

2019
Study of the acoustic noise in pipelines carrying oil products in a refinery establishment.
Proceedings of the 23rd Pan-Hellenic Conference on Informatics, 2019

Smart sensor system for leakage detection in pipes carrying oil products in noisy environment: The ESTHISIS Project.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019


Pipeline Leak Detection in Noisy Environment.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Application of the power contributors method for the AOI22 CMOS cell.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Improving the Evaluation of the Period and Amplitude of a Signal for Visually Impaired Individuals.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Learnae: Distributed and Resilient Deep Neural Network Training for Heterogeneous Peer to Peer Topologies.
Proceedings of the Engineering Applications of Neural Networks, 2019

2018
A Data-Driven Verilog-A ReRAM Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Spectrum allocation in cognitive radio networks using chaotic biogeography-based optimisation.
IET Networks, 2018

An Evaluation of the Equivalent Inverter Modeling Approach.
Circuits Syst. Signal Process., 2018

Oscilloscope Reading Device for the Visually Impaired.
Proceedings of the Technology and Innovation in Learning, Teaching and Education, 2018

Evaluation of an Artificial Neural Network Approach for Timing Modeling of CMOS Gates.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Equivalent inverter-based characterization tool for nano-scale CMOS digital cells: Non-linear-delay-models evaluation.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Software design for a sound processing embedded system.
Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

2017
A compact Verilog-A ReRAM switching model.
CoRR, 2017

An analytical delay model for ReRAM memory cells.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Cache activity profiling tool for the LEON4 processor.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

An approach for estimating adulteration of virgin olive oil with soybean oil using image analysis.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017


Live demonstration: A TiO2 ReRAM parameter extraction method.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Hot carrier degradation modeling of short-channel n-FinFETs suitable for circuit simulators.
Microelectron. Reliab., 2016

2015
Modeling leakage currents of different CMOS cells by the power contributors method.
Proceedings of the 19th Panhellenic Conference on Informatics, 2015

A study for replacing CMOS gates by equivalent inverters.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Modeling CMOS Gates Using Equivalent Inverters.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014
Real-Time Machine Vision FPGA Implementation for Microfluidic Monitoring on Lab-on-Chips.
IEEE Trans. Biomed. Circuits Syst., 2014

Design space exploration tools for the ByoRISC configurable processor family.
CoRR, 2014

An analytical model for the CMOS inverter.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Variability of nanoscale triple gate FinFETs: Prediction and analysis method.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

A unified CMOS inverter model for planar and FinFET nanoscale technologies.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013
A Digital Nonautonomous Chaotic Oscillator Suitable for Information Transmission.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

High performance median FPGA implementation for machine vision applications.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

An efficient model of the CMOS inverter for nanometer technologies.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
FPGA-based machine vision implementation for Lab-on-Chip flow detection.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Estimating the starting point of conduction in nanoscale CMOS gates.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

High speed FPGA implementation of hough transform for real-time applications.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Pass Transistor Operation Modeling for Nanoscale Technologies.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

ILP formulation for hybrid FPGA MPSoCs optimizing performance, area and memory usage.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
Design space exploration for FPGA-based multiprocessing systems.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Real-time canny edge detection parallel implementation for FPGAs.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators.
IEEE Trans. Very Large Scale Integr. Syst., 2009

An Application Development Framework for ARISE Reconfigurable Processors.
ACM Trans. Reconfigurable Technol. Syst., 2009

Scalable register bypassing for FPGA-based processors.
Microprocess. Microsystems, 2009

Input mapping algorithm for parallel transistor structures.
Int. J. Circuit Theory Appl., 2009

An integer linear programming model for mapping applications on hybrid systems.
IET Comput. Digit. Tech., 2009

2008
Energy Consumption Estimation in Embedded Systems.
IEEE Trans. Instrum. Meas., 2008

Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors.
IEEE Trans. Computers, 2008

ARISE Machines: Extending Processors with Hybrid Accelerators.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Development of a customized processor architecture for accelerating genetic algorithms.
Microprocess. Microsystems, 2007

Analysing the operation of the basic pass transistor structure.
Int. J. Circuit Theory Appl., 2007

The ARISE Reconfigurable Instruction Set Extensions Framework.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

2006
Measurement of Power Consumption in Digital Systems.
IEEE Trans. Instrum. Meas., 2006

Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications.
J. Low Power Electron., 2006

A portable specification of zero-overhead looping control hardware applied to embedded processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An automated development framework for a RISC processor with reconfigurable instruction set extensions.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
A complete platform and toolset for system implementation on fine-grain reconfigurable hardware.
Microprocess. Microsystems, 2005

Instruction level energy modeling for pipelined processors.
J. Embed. Comput., 2005

The effect of Data-Reuse Transformations on Multimedia Applications for Application Specific Processors.
Int. J. Comput., 2005

A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications.
IEICE Trans. Inf. Syst., 2005

Developing an environment for embedded software energy estimation.
Comput. Stand. Interfaces, 2005

Energy-Aware System-on-Chip for 5 GHz Wireless LANs.
Proceedings of the Integrated Circuit and System Design, 2005

Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications.
Proceedings of the 2005 Design, 2005

AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video Encoding.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Measurements analysis of the software-related power consumption in microprocessors.
IEEE Trans. Instrum. Meas., 2004

Evaluating Power Efficient Data-Reuse Decisions For Embedded Multimedia Applications: An Analytical Approach.
J. Circuits Syst. Comput., 2004

The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms.
Proceedings of the Integrated Circuit and System Design, 2004

Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform.
Proceedings of the Integrated Circuit and System Design, 2004

Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors.
Proceedings of the Integrated Circuit and System Design, 2004

The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems.
Proceedings of the Integrated Circuit and System Design, 2004

An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003
Measurement of current variations for the estimation of software-related power consumption [embedded processing circuits].
IEEE Trans. Instrum. Meas., 2003

A Methodology for Calculating the Undetectable Double-Faults in Self-Checking Circuits.
J. Circuits Syst. Comput., 2003

Tradeoffs in the Design Space Exploration of Application-Specific Processors.
Proceedings of the IFIP VLSI-SoC 2003, 2003

FPGA Architecture Design and Toolset for Logic Implementation.
Proceedings of the Integrated Circuit and System Design, 2003

2002
Efficient output waveform evaluation of a CMOS inverter based on short-circuit current prediction.
Int. J. Circuit Theory Appl., 2002

Instruction-level power consumption estimation of embedded processors for low-power applications.
Comput. Stand. Interfaces, 2002

Output Waveform Evaluation of Basic Pass Transistor Structure.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Instrumentation Set-up for Instruction Level Power Modeling.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Confronting violations of the TSCG(T) in low-power design.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Parametric architecture for implementing multimedia algorithms.
Proceedings of the 14th International Conference on Digital Signal Processing, 2002

2001
Memory hierarchy exploration for low power architectures in embedded multimedia applications.
Proceedings of the 2001 International Conference on Image Processing, 2001

Power reduction for multimedia applications through data-reuse memory exploration.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Power exploration of parallel embedded architectures implementing data-reuse transformations.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Analytical exploration of power efficient data-reuse transformations on multimedia applications.
Proceedings of the IEEE International Conference on Acoustics, 2001

2000
Estimation of signal transition activity in FIR filters implementedby a MAC architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1999
A modeling technique for CMOS gates.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

A Charge Recycling Technique for the Design of Low Power CMOS Clock Drivers.
J. Circuits Syst. Comput., 1999

Analytical estimation of propagation delay and short‐circuit power dissipation in CMOS gates.
Int. J. Circuit Theory Appl., 1999

CMOS gate modeling based on equivalent inverter.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Estimation of the transition activity in MAC architectures implementing FIR filters.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Fault secure binary counter design.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Hardware and Power Requirements of Self-checking circuits.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Single transistor primitive for modeling CMOS gates.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices.
IEEE J. Solid State Circuits, 1998

Analytical Model for the CMOS Short-Circuit Power Dissipation.
Integr. Comput. Aided Eng., 1998

Accurate calculation of bit-level transition activity using word-level statistics and entropy function.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Collapsing the Transistor Chain to an Effective Single Equivalent Transistor.
Proceedings of the 1998 Design, 1998

Switching Response Modeling of the CMOS Inverter for Sub-micron Devices.
Proceedings of the 1998 Design, 1998

1996
Accurate evaluation of CMOS short-circuit power dissipation for short-channel devices.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

CORDIC versus conventional logic for realisation of normalised lattice all-pass filters.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

Accurate timing model for the CMOS inverter.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1994
Array processor for block adaptive LS FIR filtering.
Signal Process., 1994

1993
Real time Cepstrum computation based on an Advanced CORDIC processor.
Microprocess. Microprogramming, 1993

Implementation of Given's Rotation processors for DSP real-time applications.
Microprocess. Microprogramming, 1993

Development of a technology independent library.
Microprocess. Microprogramming, 1993

CORDIC Based Pipeline Architecture for All-pass Filters.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992
A processor for time-varying digital audio filters with special transition properties.
Proceedings of the Fourth Euromicro workshop on Real-Time Systems, 1992

1991
Array processor for LS FIR system identification.
Microprocessing and Microprogramming, 1991


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