Abdus Sami Hassan

Orcid: 0000-0001-5392-3595

According to our database1, Abdus Sami Hassan authored at least 10 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Low Latency and High Throughput Pipelined Online Adder for Streaming Inner Product.
J. Signal Process. Syst., July, 2023

On the Evolutionary Synthesis of Fault-Resilient Digital Circuits.
IEEE Trans. Evol. Comput., April, 2023

2021
Adder with Reduced Latency and Minimized Interconnect for Streaming Inner Products.
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021

2020
Improved error detection performance of logic implication checking in FPGA circuits.
Microprocess. Microsystems, 2020

Approximate Triple Modular Redundancy: A Survey.
IEEE Access, 2020

Data Footprint Reduction in DNN Inference by Sensitivity-Controlled Approximations with Online Arithmetic.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2018
Generation Methodology for Good-Enough Approximate Modules of ATMR.
J. Electron. Test., 2018

Error Correctable Approximate Multiplier with Area/Power Efficient Design Through Mixed CMOS/PTL.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Effect of FPGA Circuit Implementation on Error Detection Using Logic Implication Checking.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2016
Probing Approximate TMR in Error Resilient Applications for Better Design Tradeoffs.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016


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