Jeong-A Lee
Orcid: 0000-0002-5166-0629Affiliations:
- Chosun University, Department of Computer Engineering, Gwangju, South Korea
- University of Houston, Department of Electrical Engineering, TX, USA
According to our database1,
Jeong-A Lee
authored at least 82 papers
between 1991 and 2023.
Collaborative distances:
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Online presence:
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on orcid.org
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on chosun.ac.kr
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Bibliography
2023
A Parallel Prefix Modulo-(2<sup>q</sup> + 2<sup>q-1</sup> + 1) Adder via Diminished-1 Representation of Residues.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
Low-Latency Online Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays.
J. Signal Process. Syst., July, 2023
J. Signal Process. Syst., July, 2023
Fuzzy logic-based DDoS attacks and network traffic anomaly detection methods: Classification, overview, and future perspectives.
Inf. Sci., May, 2023
IEEE Trans. Evol. Comput., April, 2023
A fast MILP solver for high-level synthesis based on heuristic model reduction and enhanced branch and bound algorithm.
J. Supercomput., 2023
A new energy-efficient and temperature-aware routing protocol based on fuzzy logic for multi-WBANs.
Ad Hoc Networks, 2023
Dependable DNN Accelerator for Safety-Critical Systems: A Review on the Aging Perspective.
IEEE Access, 2023
Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2023
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
Modulo-(2<sup>q</sup> - 3) Multiplication with Fully Modular Partial Product Generation and Reduction.
Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023
Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023
An Efficient Dot-Product Unit Based on Online Arithmetic for Variable Precision Applications.
Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023
2022
An improved discrete harris hawk optimization algorithm for efficient workflow scheduling in multi-fog computing.
Sustain. Comput. Informatics Syst., 2022
IEEE Access, 2022
kNN-MSDF: A Hardware Accelerator for k-Nearest Neighbors Using Most Significant Digit First Computation.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Proceedings of the 6th International Conference on Video and Image Processing, 2022
An Energy-Efficient K-means Clustering FPGA Accelerator via Most-Significant Digit First Arithmetic.
Proceedings of the International Conference on Field-Programmable Technology, 2022
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022
2021
Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays.
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021
2020
A Computerized Bioinspired Methodology for Lightweight and Reliable Neural Telemetry.
Sensors, 2020
Microprocess. Microsystems, 2020
AMC-IoT: Automatic Modulation Classification Using Efficient Convolutional Neural Networks for Low Powered IoT Devices.
Proceedings of the International Conference on Information and Communication Technology Convergence, 2020
Proceedings of the International Conference on Information and Communication Technology Convergence, 2020
Data Footprint Reduction in DNN Inference by Sensitivity-Controlled Approximations with Online Arithmetic.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
2019
DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Design and Performance Evaluation of a Low-Cost Autonomous Sensor Interface for a Smart IoT-Based Irrigation Monitoring and Control System.
Sensors, 2019
AFP-CKSAAP: Prediction of Antifreeze Proteins Using Composition of k-Spaced Amino Acid Pairs with Deep Neural Network.
Proceedings of the 19th IEEE International Conference on Bioinformatics and Bioengineering, 2019
2018
SEDC-Based Hardware-Level Fault Tolerance and Fault Secure Checker Design for Big Data and Cloud Computing.
Sci. Program., 2018
J. Electron. Test., 2018
IEEE Access, 2018
High-Speed Configuration Strategy for Configurable Logic Block-Based TCAM Architecture on FPGA.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Error Correctable Approximate Multiplier with Area/Power Efficient Design Through Mixed CMOS/PTL.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Effect of FPGA Circuit Implementation on Error Detection Using Logic Implication Checking.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
2017
Efficient Low-Cost Fault-Localization and Self-Repairing Radix-2 Signed-Digit Adders Applying the Self-Dual Concept.
J. Signal Process. Syst., 2017
Bio-inspired self-aware fault-tolerant routing protocol for network-on-chip architectures using Particle Swarm Optimization.
Microprocess. Microsystems, 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
2016
Self-repairing radix-2 signed-digit adder with multiple error detection, correction, and fault localization.
Microelectron. Reliab., 2016
FPGA-Based Design of an Intelligent On-Chip Sensor Network Monitoring and Control Using Dynamically Reconfigurable Autonomous Sensor Agents.
Int. J. Distributed Sens. Networks, 2016
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
2015
An Autonomous Self-Aware and Adaptive Fault Tolerant Routing Technique for Wireless Sensor Networks.
Sensors, 2015
Secur. Commun. Networks, 2015
Multim. Tools Appl., 2015
Low-Cost Fault Localization and Error Correction for a Signed Digit Adder Design Utilizing the Self-Dual Concept.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip.
Microprocess. Microsystems, 2014
2013
A novel run-time auto-reconfigurable FPGA architecture for fast fault recovery with backward compatibility (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2012
Proceedings of the Second ACM Workshop on Mobile Systems, 2012
Proceedings of the International Conference on Information and Communication Technology Convergence, 2012
An island-style-routing compatible fault-tolerant FPGA architecture with self-repairing capabilities.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
2010
Reconfiguration for Sensitivity Technique: A QoS-aware Co-Design approach for stream-based applications.
IEICE Electron. Express, 2010
Proceedings of the 9th IEEE/ACIS International Conference on Computer and Information Science, 2010
2009
Exploration of Power-Delay Trade-Offs with Heterogeneous Adders by Integer Linear Programming.
J. Circuits Syst. Comput., 2009
IEICE Electron. Express, 2009
2007
Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions.
J. VLSI Signal Process., 2007
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007
2005
IEICE Trans. Inf. Syst., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Electron., 2005
Self-timed Interconnect with Layered Interface Based on Distributed and Modularized Control for Multimedia SoCs.
Proceedings of the Advances in Multimedia Information Processing, 2005
High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
2004
Proceedings of the Intenational Symposium on Information and Communication Technologies, 2004
Operation Net System: A Formal Design Representation Model for High-Level Synthesis of Asynchronous Systems Based on Transformations.
Proceedings of the Applications and Theory of Petri Nets 2004, 2004
Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space Localization.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004
High Performance Microprocessor Design Methods Exploiting Information Locality and Data Redundancy for Lower Area Cost and Power Consumption.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004
Heuristic Algorithm for Reducing Mapping Sets of Hardware-Software Partitioning in Reconfigurable System.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004
2003
Design and Evaluation of a Cache Coherence Adapter for the SMP Nodes Interconnected via Xcent-Net.
Proceedings of the Computer and Information Sciences, 2003
Producer and Consumer: Roles of a Microprocessor and a Configurable Logic in a Configurable SoC.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003
2000
J. VLSI Signal Process., 2000
1994
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994
1992
IEEE Trans. Computers, 1992
1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
Proceedings of the First Great Lakes Symposium on VLSI, 1991
Proceedings of the 10th IEEE Symposium on Computer Arithmetic, 1991