Milos D. Ercegovac

According to our database1, Milos D. Ercegovac authored at least 122 papers between 1972 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2003, "For contributions to the theory and practice of digital arithmetic.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2017
On left-to-right arithmetic.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
An Energy-Efficient Multiplier With Fully Overlapped Partial Products Reduction and Final Addition.
IEEE Trans. on Circuits and Systems, 2016

Radix-4 energy efficient carry-free truncated multiplier.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016

2015
An error-compensated piecewise linear logarithmic arithmetic unit for phong lighting acceleration.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014
(M, p, k)-Friendly Points: A Table-Based Method to Evaluate Trigonometric Function.
IEEE Trans. on Circuits and Systems, 2014

Complex Function Approximation Using Two-Dimensional Interpolation.
IEEE Trans. Computers, 2014

Low-power radix-4 quotient generator.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
Energy-efficient computing using adaptive table lookup based on nonvolatile memories.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Power optimization in a parallel multiplier using voltage islands.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Power optimization of sum-of-products design for signal processing applications.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

On approximate arithmetic.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
A Radix-16 Combined Complex Division/Square Root Unit with Operand Prescaling.
IEEE Trans. Computers, 2012

(M, p, k)-Friendly Points: A Table-Based Method for Trigonometric Function Evaluation.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

Shared implementation of radix-10 and radix-16 square root algorithm with limited precision primitives.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

Session TP8a3: Design methodology and computer arithmetic.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

Linearization using efficient complex polynomial evaluations.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
Trading Accuracy for Power in a Multiplier Architecture.
J. Low Power Electronics, 2011

Trading Accuracy for Power with an Underdesigned Multiplier Architecture.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Accelerating the photon mapping algorithm and its hardware implementation.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

Shared implementation of radix-10 and radix-16 division algorithm with limited precision primitives.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010
An Efficient Method for Evaluating Complex Polynomials.
Signal Processing Systems, 2010

Design of High-Throughput Fixed-Point Complex Reciprocal/Square-Root Unit.
IEEE Trans. on Circuits and Systems, 2010

Combining leak-resistant arithmetic for elliptic curves defined over Fp and RNS representation.
IACR Cryptology ePrint Archive, 2010

Implementing decimal floating-point arithmetic through binary: Some suggestions.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009
Exploration of Power-Delay Trade-Offs with Heterogeneous Adders by Integer Linear Programming.
Journal of Circuits, Systems, and Computers, 2009

A radix-8 complex divider for FPGA implementation.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Design and Implementation of a Radix-4 Complex Division Unit with Prescaling.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008
Digital Arithmetic.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

An efficient method for evaluating polynomial and rational function approximations.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007
Complex Square Root with Operand Prescaling.
VLSI Signal Processing, 2007

The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration.
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

A Design Method for Heterogeneous Adders.
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007

A Hardware-Oriented Method for Evaluating Complex Polynomials.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2005
High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation.
VLSI Signal Processing, 2005

High-Performance Low-Power Left-to-Right Array Multiplier Design.
IEEE Trans. Computers, 2005

RAVIOLI - Reconfigurable Arithmetic Variable-Precision Implementations of On-Line Instructions.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Variable Radix Real and Complex Digit-Recurrence Division.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

A Linear-System Operator Based Scheme for Evaluation of Multinomials.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004
Algorithm and Architecture for Logarithm, Exponential, and Powering Computation.
IEEE Trans. Computers, 2004

From the University of Illinois via JPL and UCLA to Vytautas Magnus University - 50 years of computer engineering by Algirdas Avizienis.
Proceedings of the Building the Information Society, 2004

Complex Square Root with Operand Prescaling.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
Performance-driven mapping for CPLD architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

On-line high-radix exponential with selection by rounding.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

High-Radix Iterative Algorithm for Powering Computation.
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

High-Performance Left-to-Right Array Multiplier Design.
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

2002
High-Level Synthesis with SIMD Units.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Two-dimensional signal gating for low-power array multiplier design.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

High-Radix Logarithm with Selection by Rounding.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001
A FPGA-based Library for On-Line Signal Processing.
VLSI Signal Processing, 2001

Performance-driven mapping for CPLD architectures.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

FPGA Implementation of Pipelined On-Line Scheme for 3-D Vector Normalization.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

2000
Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers.
IEEE Trans. Computers, 2000

Improving Goldschmidt Division, Square Root, and Square Root Reciprocal.
IEEE Trans. Computers, 2000

A Component Framework for Communication in Distributed Applications.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

BigSky-An On-Line Arithmetic Design Tool for FPGAs.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999
FPGA-Based Structures for On-Line FFT and DCT.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

Low-Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic.
Proceedings of the 36th Conference on Design Automation, 1999

On the Design of High-Radix On-Line Division for Long Precision.
Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

1998
Long and Fast Up/Down Counters.
IEEE Trans. Computers, 1998

Behavioral synthesis optimization using multiple precision arithmetic.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1997
Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency Independent of Counter Size.
Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

1996
On recoding in arithmetic algorithms.
VLSI Signal Processing, 1996

Vector quantization with variable-precision classification.
IEEE Trans. Image Processing, 1996

Vector quantization with compressed codebooks.
Sig. Proc.: Image Comm., 1996

1995
A variable-precision square root implementation for field programmable gate arrays.
The Journal of Supercomputing, 1995

Sign detection and comparison networks with a small number of transitions.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1994
Implementing division with field programmable gate arrays.
VLSI Signal Processing, 1994

Conventional and on-line arithmetic designs for high-speed recursive digital filters.
VLSI Signal Processing, 1994

Very-High Radix Division with Prescaling and Selection by Rounding.
IEEE Trans. Computers, 1994

1993
Multiplication/ division/ square root module for massively parallel computers.
Integration, 1993

ALIAS Environment: A Design Tool for Application Specific Arrays.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

Symbolic Synthesis of Parallel Processing Systems.
Proceedings of the Seventh International Parallel Processing Symposium, 1993

On digit-recurrence division implementations for field programmable gate arrays.
Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993

Very high radix division with selection by rounding and prescaling.
Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993

1992
On-the-Fly Rounding.
IEEE Trans. Computers, 1992

A methodology for performance analysis of parallel computations with looping constructs.
J. Parallel Distrib. Comput., 1992

Architectural Support for Goal Management in Flat Concurrent Prolog.
IEEE Computer, 1992

Variable Precision Representation for Efficient VQ Codebook Storage.
Proceedings of the IEEE Data Compression Conference, 1992

1991
Gate array implementation of on-line algorithms for floating-point operations.
VLSI Signal Processing, 1991

Module to Perform Multiplication, Division, and Square Root in Systolic Arrays for Matrix Computations.
J. Parallel Distrib. Comput., 1991

Application of on-line arithmetic algorithms to the SVD computation: preliminary results.
Proceedings of the 10th IEEE Symposium on Computer Arithmetic, 1991

1990
Fast Multiplication Without Carry-Propagate Addition.
IEEE Trans. Computers, 1990

Simple Radix-4 Division with Opterands Scaling.
IEEE Trans. Computers, 1990

Radix-4 Square Root Without Initial PLA.
IEEE Trans. Computers, 1990

Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD.
IEEE Trans. Computers, 1990

Architectural Support for the Management of Tightly-Coupled Fine-Grain Goals in Flat Concurrent Prolog.
Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990

1989
A Modeling Methodology for the Analysis of Concurrent Systems and Computations.
J. Parallel Distrib. Comput., 1989

Design of on-line division unit.
Proceedings of the 9th Symposium on Computer Arithmetic, 1989

On-the-fly rounding for division and square root.
Proceedings of the 9th Symposium on Computer Arithmetic, 1989

Radix-4 square root without initial PLA.
Proceedings of the 9th Symposium on Computer Arithmetic, 1989

Design of an on-line multiply-add module for recursive digital filters.
Proceedings of the 9th Symposium on Computer Arithmetic, 1989

1988
Heterogeneity in supercomputer architectures.
Parallel Computing, 1988

On-Line Scheme for Computing Rotation Factors.
J. Parallel Distrib. Comput., 1988

1987
On-the-Fly Conversion of Redundant into Conventional Representations.
IEEE Trans. Computers, 1987

A radix-4 on-line division algorithm.
Proceedings of the 8th IEEE Symposium on Computer Arithmetic, 1987

On-line scheme for computing rotation factors.
Proceedings of the 8th IEEE Symposium on Computer Arithmetic, 1987

1985
Performance evaluation of a simulated data-flow computer with low-resolution actors.
J. Parallel Distrib. Comput., 1985

vFP: An Environment for the Multi-level Specification, Analysis, and Synthesis of Hardware Algorithms.
Proceedings of the Functional Programming Languages and Computer Architecture, 1985

A functional language for description and design of digital systems: sequential constructs.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

A division algorithm with prediction of quotient digits.
Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985

1984
Fault Tolerance in Binary Tree Architectures.
IEEE Trans. Computers, 1984

Performance Analysis of a Data-Flow Computer with Variable Resolution Actors.
Proceedings of the 4th International Conference on Distributed Computing Systems, 1984

1983
Error Analysis of Certain Floating-Point On-Line Algorithms.
IEEE Trans. Computers, 1983

On-line multiplicative normalization.
Proceedings of the 6th IEEE Symposium on Computer Arithmetic, 1983

A higher-radix division with simple selection of quotient digits.
Proceedings of the 6th IEEE Symposium on Computer Arithmetic, 1983

1982
A On-Line Square Root Algorithm.
IEEE Trans. Computers, 1982

A scheme for handling arrays in data-flow systems.
Proceedings of the Proceedings of the 3rd International Conference on Distributed Computing Systems, 1982

1981
Queue machines: an organization for parallel computation.
Proceedings of the CONPAR 81: Conference on Analysing Problem Classes and Programming for Parallel Computing, 1981

Floating-point on-line arithmetic: Error analysis.
Proceedings of the 5th IEEE Symposium on Computer Arithmetic, 1981

Floating-point on-line arithmetic: Algorithms.
Proceedings of the 5th IEEE Symposium on Computer Arithmetic, 1981

A simulator for on-line arithmetic.
Proceedings of the 5th IEEE Symposium on Computer Arithmetic, 1981

Design of a digit-slice on-line arithmetic unit.
Proceedings of the 5th IEEE Symposium on Computer Arithmetic, 1981

1978
An arithmetic module for efficient evaluation of functions.
Proceedings of the 4th IEEE Symposium on Computer Arithmetic, 1978

An on-line square rooting algorithm.
Proceedings of the 4th IEEE Symposium on Computer Arithmetic, 1978

1977
On-Line Algorithms for Division and Multiplication.
IEEE Trans. Computers, 1977

A General Hardware-Oriented Method for Evaluation of Functions and Computations in a Digital Computer.
IEEE Trans. Computers, 1977

1975
On-line algorithms for division and multiplication.
Proceedings of the 3rd IEEE Symposium on Computer Arithmetic, 1975

A general method for evaluation of functions and computations in a digital computing.
Proceedings of the 3rd IEEE Symposium on Computer Arithmetic, 1975

1973
Radix-16 Evaluation of Certain Elementary Functions.
IEEE Trans. Computers, 1973

1972
Eadix l6 evaluation of some elementary functions.
Proceedings of the 2nd IEEE Symposium on Computer Arithmetic, 1972


  Loading...