Abhishek Bandyopadhyay

According to our database1, Abhishek Bandyopadhyay authored at least 20 papers between 2002 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Common-mode Stable Multilevel Output Stage with EMI Reduction Feedback Loop for Class-D audio Amplifier.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
An 82-mW ΔΣ-Based Filter-Less Class-D Headphone Amplifier With -93-dB THD+N, 113-dB SNR, and 93% Efficiency.
IEEE J. Solid State Circuits, 2021

31.1 An 82mW ΔΣ - Based Filter-Less Class-D Headphone Amplifier with -93dB THD+N, 113dB SNR and 93% Efficiency.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2019
An offline scheme for reducing cost of protection in all-optical WDM mesh networks with fast recovery.
Int. J. Parallel Emergent Distributed Syst., 2019

2015
Session 18 - Data converter techniques.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Improved algorithms for dynamic routing and wavelength assignment in WDM all-optical mesh networks.
Proceedings of the Eleventh International Conference on Wireless and Optical Communications Networks, 2014

A 97.3 dB SNR, 600 kHz BW, 31mW multibit continuous time ΔΣ ADC.
Proceedings of the Symposium on VLSI Circuits, 2014

Dynamic survivable traffic grooming with effective load balancing in WDM all-optical mesh networks.
Proceedings of the 2014 International Conference on Advances in Computing, 2014

2011
A 120dB-SNR 100dB-THD+N 21.5mW/channel multibit CT ΔΣ DAC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2008
A 108 dB SNR, 1.1 mW Oversampling Audio DAC With A Three-level DEM Technique.
IEEE J. Solid State Circuits, 2008

A 108dB SNR 1.1mW Oversampling Audio DAC with a Three-Level DEM Technique.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006
Adaptive Algorithm Using Hot-Electron Injection for Programming Analog Computational Memory Elements Within 0.2% of Accuracy Over 3.5 Decades.
IEEE J. Solid State Circuits, 2006

MATIA: a programmable 80 WμW/frame CMOS block matrix transform imager architecture.
IEEE J. Solid State Circuits, 2006

2005
Programming analog computational memory elements to 0.2% accuracy over 3.5 decades using a predictive method.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 80µW/frame 104×128 CMOS imager front end for JPEG compression.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Image processing system using a programmable transform imager.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

2004
A 531 nW/MHz, 128×32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
High Fill-Factor Imagers for Neuromorphic Processing Enabled by Floating-Gate Circuits.
EURASIP J. Adv. Signal Process., 2003

A fully programmable CMOS block matrix transform imager architecture.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
A matrix transform imager allowing high-fill factor.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002


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