Ismail Faik Baskaya

Orcid: 0000-0001-6743-3992

Affiliations:
  • Bogaziçi University, Electrical and Electronics Engineering, Istanbul, Turkey
  • Georgia Institute of Technology, Atlanta, GA, USA (PhD 2009)


According to our database1, Ismail Faik Baskaya authored at least 33 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2023
Jitter Modeling for High Precision Frequency Measurements in Oscillator Circuits.
Proceedings of the 19th International Conference on Synthesis, 2023

2022
PLL Based Synchronous Read-Out for Resonant Biosensors.
Proceedings of the 30th Signal Processing and Communications Applications Conference, 2022

2021
Convolutional Neural Network-Based Signal Classification in Real Time.
IEEE Embed. Syst. Lett., 2021

ACTreS: Analog Clock Tree Synthesis.
CoRR, 2021

2020
A modified relay-race algorithm for floorplanning in PCB and IC design.
Turkish J. Electr. Eng. Comput. Sci., 2020

2019
On Chip Reconfigurable CMOS Analog Circuit Design and Automation Against Aging Phenomena: Sense and React.
ACM Trans. Design Autom. Electr. Syst., 2019

2018
A Rare Event Based Yield Estimation Methodology for Analog Circuits.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017
Aging signature properties and an efficient signature determination tool for online monitoring.
Integr., 2017

2016
An analog circuit synthesis tool based on efficient and reliable yield estimation.
Microelectron. J., 2016

A lifetime-aware analog circuit sizing tool.
Integr., 2016

Semi-empirical aging model development via accelerated aging test.
Proceedings of the 13th International Conference on Synthesis, 2016

2015
A two-step layout-in-the-loop design automation tool.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

A novel yield aware multi-objective analog circuit optimization tool.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Design of blocks for a Field Programmable Mixed Array (FPMA).
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

A hybrid Quasi Monte Carlo method for yield aware analog circuit sizing tool.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Reliability assessment of CMOS differential cross-coupled LC oscillators and a novel on chip self-healing approach against aging phenomena.
Microelectron. Reliab., 2014

Model based hierarchical optimization strategies for analog design automation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Analog layer extensions for analog/mixed-signal assertion languages.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Integrating circuit analyses for assertion-based verification of programmable AMS circuits.
Proceedings of the 2013 Forum on specification and Design Languages, 2013

Synthesis of clock trees for Sampled-Data Analog IC blocks.
Proceedings of the East-West Design & Test Symposium, 2013

2012
High-Level verifiable data-path Synthesis for DSP systems.
Proceedings of the 20th Signal Processing and Communications Applications Conference, 2012

A Verifiable High Level Data Path Synthesis Framework.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2010
A Floating-Gate-Based Field-Programmable Analog Array.
IEEE J. Solid State Circuits, 2010

2009
Physical design automation for large scale field programmable analog arrays.
PhD thesis, 2009

Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A generic reconfigurable array specification and programming environment (GRASPER).
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2007
A Self-Contained Large-Scale FPAA Development Platform.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

2006
Placement for large-scale floating-gate field-programable analog arrays.
IEEE Trans. Very Large Scale Integr. Syst., 2006

2005
Mapping algorithm for large-scale field programmable analog array.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Image processing system using a programmable transform imager.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

Hierarchical Placement for Large-scale FPAA.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

A single chip solution for text-to-speech synthesis.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005


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