Abu Asaduzzaman

Orcid: 0000-0002-5041-1575

According to our database1, Abu Asaduzzaman authored at least 35 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

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Bibliography

2023
3D layout of the Spidergon-Donut on-chip interconnection network.
Int. J. High Perform. Syst. Archit., 2023

Modeling and Analyzing Wind Velocity at Entrance Doors to Avoid Accidents.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2023

2022
Hardware Acceleration of the STRIKE String Kernel Algorithm for Estimating Protein to Protein Interactions.
IEEE ACM Trans. Comput. Biol. Bioinform., 2022

2021
Energy Consumption Analyses for Unmanned Aerial Systems used in Disaster Management.
Proceedings of the 11th IEEE Annual Computing and Communication Workshop and Conference, 2021

Studying Execution Time and Memory Transfer Time of Image Processing Using GPU Cards.
Proceedings of the 11th IEEE Annual Computing and Communication Workshop and Conference, 2021

Smart Disaster Management Using Software-Defined Unmanned Aerial Systems.
Proceedings of the 18th IEEE Annual Consumer Communications & Networking Conference, 2021

2019
Impact of Non-Uniform Subnets on the Performance of Wireless Network-on-Chip Architectures.
Proceedings of the IEEE 9th Annual Computing and Communication Workshop and Conference, 2019

Shared Entry Logger to Eliminate Duplicate Requests to SDN Controller.
Proceedings of the IEEE 9th Annual Computing and Communication Workshop and Conference, 2019

Dedicated Backup Units to Alleviate Overload on SDN Controllers.
Proceedings of the IEEE 9th Annual Computing and Communication Workshop and Conference, 2019

Introducing Edge Controlling to Software Defined Networking to Reduce Processing Time.
Proceedings of the IEEE 9th Annual Computing and Communication Workshop and Conference, 2019

2018
A promising security protocol for protecting near field communication devices from networking attacks.
Int. J. Secur. Networks, 2018

A novel Wireless Network-on-Chip architecture with distributed directories for faster execution and minimal energy.
Comput. Electr. Eng., 2018

Distribution Model for OpenFlow-Based Networks.
Proceedings of the 9th IEEE Annual Ubiquitous Computing, 2018

2017
An Energy-Efficient Directory Based Multicore Architecture with Wireless Routers to Minimize the Communication Latency.
IEEE Trans. Parallel Distributed Syst., 2017

A security-aware Near Field Communication architecture.
Proceedings of the International Conference on Networking, Systems and Security, 2017

2016
An auspicious secure processing technique for near field communication systems.
Proceedings of the 7th IEEE Annual Ubiquitous Computing, 2016

2014
Power and performance analysis of multimedia applications running on low-power devices by cache modeling.
Multim. Tools Appl., 2014

A promising CUDA-accelerated vehicular area network simulator using NS-3.
Proceedings of the IEEE 33rd International Performance Computing and Communications Conference, 2014

2013
A Power-Aware Multi-Level Cache Organization Effective for Multi-Core Embedded Systems.
J. Comput., 2013

On level-1 cache locking for high-performance low-power real-time multicore systems.
Comput. Electr. Eng., 2013

A novel folded-torus based network architecture for power-aware multicore systems.
Comput. Electr. Eng., 2013

Performance-power analysis of H.265/HEVC and H.264/AVC running on multicore cache systems.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2013

2012
A Way Cache Locking Scheme Supported by Knowledge Based Smart Preload Effective for Low-Power Multicore Electronics.
J. Low Power Electron., 2012

2011
A dynamic way cache locking scheme to improve the predictability of power-aware embedded systems.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
Improving cache locking performance of modern embedded systems via the addition of a miss table at the L2 cache level.
J. Syst. Archit., 2010

2009
Cache optimization for real-time embedded systems.
PhD thesis, 2009

Impact of level-2 cache sharing on the performance and power requirements of homogeneous multicore embedded systems.
Microprocess. Microsystems, 2009

Conceptual Modeling of Multicore High Performance Computing Systems.
Proceedings of the Huntsville Simulation Conference, 2009

Impact of L1 entire locking and L2 way locking on the performance, power consumption, and predictability of multicore real-time systems.
Proceedings of the 7th IEEE/ACS International Conference on Computer Systems and Applications, 2009

2007
Impacts of Level-2 Cache on Performance of Multimedia Systems and Applications.
Proceedings of the SIGMAP 2007, 2007

Performance Analysis of Scheduling-Based Load Balancing for Distributed and Parallel Systems Using Visualsim.
Proceedings of the ICSOFT 2007, 2007

2006
Cache modeling and optimization for portable devices running MPEG-4 video decoder.
Multim. Tools Appl., 2006

Cache Optimization for Embedded Systems Running H.264/AVC Video Decoder.
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006

2004
Cache optimization for mobile devices running multimedia applications.
Proceedings of the Sixth IEEE International Symposium on Multimedia Software Engineering, 2004

1998
Memory latency evaluation in cluster-based cache coherent multiprocessor with different network topologies.
Proceedings of the Computers and Their Applications (CATA-98), 1998


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