Fadi N. Sibai

Orcid: 0000-0002-9677-8911

According to our database1, Fadi N. Sibai authored at least 72 papers between 1989 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
Parallel Deployment and Performance Analysis of a Multi-Hop Routing Protocol for 5G Backhaul Networks Using Cloud and HPC Platforms.
IEEE Access, 2024

2023
Epilepsy Detection with Multi-channel EEG Signals Utilizing AlexNet.
Circuits Syst. Signal Process., November, 2023

3D layout of the Spidergon-Donut on-chip interconnection network.
Int. J. High Perform. Syst. Archit., 2023

2022
Home Automation Using Augmented Reality (HAAR).
Wirel. Pers. Commun., 2022

Hardware Acceleration of the STRIKE String Kernel Algorithm for Estimating Protein to Protein Interactions.
IEEE ACM Trans. Comput. Biol. Bioinform., 2022

2021
Energy Consumption Analyses for Unmanned Aerial Systems used in Disaster Management.
Proceedings of the 11th IEEE Annual Computing and Communication Workshop and Conference, 2021

Smart Disaster Management Using Software-Defined Unmanned Aerial Systems.
Proceedings of the 18th IEEE Annual Consumer Communications & Networking Conference, 2021

2020
PMSMC: Priority-based Multi-requestor Scheduler for Embedded System Memory Controller.
J. Parallel Distributed Comput., 2020

Deployment and Analysis of a Hybrid Shared/Distributed-Memory Parallel Visualization Tool for 3-D Oil Reservoir Grid on OpenStack Cloud Computing.
IEEE Access, 2020

AI Crimes: A Classification.
Proceedings of the 2020 International Conference on Cyber Security and Protection of Digital Services, 2020

2018
Parallel Study of 3-D Oil Reservoir Data Visualization Tool Using Hybrid Distributed/Shared-Memory Models.
Proceedings of the 2018 IEEE 16th Intl Conf on Dependable, 2018

2015
Parallel PPI Prediction Performance Study on HPC Platforms.
J. Circuits Syst. Comput., 2015

2014
Performance evaluation and comparison of parallel conjugate gradient on modern multi-core accelerator and massively parallel systems.
Int. J. Parallel Emergent Distributed Syst., 2014

Performance modeling and analysis of parallel Gaussian elimination on multi-core computers.
J. King Saud Univ. Comput. Inf. Sci., 2014

V-Set Cache: an Efficient Adaptive Shared Cache for Multi-Core Processors.
J. Circuits Syst. Comput., 2014

2013
Ear recognition with feed-forward artificial neural networks.
Neural Comput. Appl., 2013

On level-1 cache locking for high-performance low-power real-time multicore systems.
Comput. Electr. Eng., 2013

2012
A Two-Dimensional Low-Diameter Scalable On-Chip Network for Interconnecting Thousands of Cores.
IEEE Trans. Parallel Distributed Syst., 2012

Parallel Implementation and Performance Analysis of a 3D Oil Reservoir Data Visualization Tool on the Cell Broadband Engine and CUDA GPU.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

V-Set Cache Design for LLC of Multi-core Processors.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

2011
Iris recognition using artificial neural networks.
Expert Syst. Appl., 2011

Parallelization and performance comparison of the conjugate gradient equation solver on multicore Cell and Xeon computers.
Concurr. Comput. Pract. Exp., 2011

Image processing applications performance study on Cell BE and Blue Gene/L.
Concurr. Comput. Pract. Exp., 2011

Design and evaluation of low latency interconnection networks for real-time many-core embedded systems.
Comput. Electr. Eng., 2011

Parallel Orthomin Equation Solver on the Cell Broadband Engine.
Proceedings of the Sixth International Symposium on Parallel Computing in Electrical Engineering (PARELEC 2011), 2011

A dynamic way cache locking scheme to improve the predictability of power-aware embedded systems.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Conotoxin protein classification using pairwise comparison and amino acid composition: toxin-aam.
Proceedings of the 13th Annual Genetic and Evolutionary Computation Conference, 2011

2010
Improving cache locking performance of modern embedded systems via the addition of a miss table at the L2 cache level.
J. Syst. Archit., 2010

Implementation and performance analysis of parallel conjugate gradient on the Cell Broadband Engine.
IBM J. Res. Dev., 2010

Massive video-surveillance parallelization on the Cell Broadband Engine processor.
IBM J. Res. Dev., 2010

Parallel protein sequence matching on multicore computers.
Proceedings of the Second International Conference of Soft Computing and Pattern Recognition, 2010

Low Diameter Unicast On-Chip Interconnection Networks for Many-Core Embedded Systems.
Proceedings of the CISIS 2010, 2010

Simulation and Performance Analysis of Multi-core Thread Scheduling and Migration Algorithms.
Proceedings of the CISIS 2010, 2010

Which On-Chip Interconnection Network for 16-core MPSoCs?.
Proceedings of the CISIS 2010, 2010

2009
Parallel Simulation of Oil Reservoirs on a Multi-core Stream Computer.
Trans. Comput. Sci., 2009

Impact of level-2 cache sharing on the performance and power requirements of homogeneous multicore embedded systems.
Microprocess. Microsystems, 2009

Parallelization and Performance Evaluation of an Edge Detection Algorithm on a Streaming Multi-Core Engine.
J. Inf. Technol. Res., 2009

Parallel Video Processing Performance Evaluation on the IBM Cell Broadband Engine Processor.
Int. J. Comput. Sci. Appl., 2009

Resource Sharing in Networks-on-Chip of Large Many-core Embedded Systems.
Proceedings of the ICPPW 2009, 2009

Parallelization and Performance Analysis of an IMPES-based Oil-Water Reservoir Simulator.
Proceedings of the 11th IEEE International Conference on High Performance Computing and Communications, 2009

Parallel Video Surveillance on the Multi-core Cell Broadband Engine.
Proceedings of the Second International Joint Conference on Computational Sciences and Optimization, 2009

Highly parallel image processing on the STI Cell.
Proceedings of the 7th IEEE/ACS International Conference on Computer Systems and Applications, 2009

Impact of L1 entire locking and L2 way locking on the performance, power consumption, and predictability of multicore real-time systems.
Proceedings of the 7th IEEE/ACS International Conference on Computer Systems and Applications, 2009

2008
Evaluating the performance of single and multiple core processors with PCMARK®05 and benchmark analysis.
SIGMETRICS Perform. Evaluation Rev., 2008

On the performance benefits of sharing and privatizing second and third-level cache memories in homogeneous multi-core architectures.
Microprocess. Microsystems, 2008

Area-efficient floorplans and interconnects for homogeneous multi-core architectures.
Int. J. High Perform. Syst. Archit., 2008

A Cross-Layer Design Framework using Functional Components.
Int. J. Bus. Data Commun. Netw., 2008

Adapting the Hyper-Ring Interconnect for Many-Core Processors.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008

Gauging the OpenSourceMark Benchmark in Measuring CPU Performance.
Proceedings of the 7th IEEE/ACIS International Conference on Computer and Information Science, 2008

2007
Performance analysis and workload characterization of the 3DMark05 benchmark on modern parallel computer platforms.
SIGARCH Comput. Archit. News, 2007

3D Graphics Performance Scaling and Workload Decomposition and Analysis.
Proceedings of the 6th Annual IEEE/ACIS International Conference on Computer and Information Science (ICIS 2007), 2007

1999
Optimal Clustering of Hierarchical Hyper-Ring Multicomputers.
J. Supercomput., 1999

Message from the PERH Workshop Co-Chairs.
Proceedings of the 1999 International Conference on Parallel Processing Workshops, 1999

1998
The hyper-ring network: a cost-efficient topology for scalable multicomputers.
Proceedings of the 1998 ACM symposium on Applied Computing, 1998

Performance of the hyper-ring multicomputer.
Proceedings of the 1998 ACM symposium on Applied Computing, 1998

1997
A time-multiplexed reconfigurable neuroprocessor.
IEEE Micro, 1997

Distributed routing in the recursive diamond network.
Proceedings of the 1997 ACM symposium on Applied Computing, 1997

On the impact of pipelined communication in hierarchical ring multicomputers.
Proceedings of the 1997 ACM symposium on Applied Computing, 1997

Multi-node communication in hyper-ring networks.
Proceedings of the 1997 ACM symposium on Applied Computing, 1997

1996
A Processor Allocation Strategy for Full-Cube Multicomputers.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996

Construction and Properties of the Recursive Diamond Multicomputer.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996

1994
Comparison of Reconfiguration Schemes for the C2SC MIN Operating in the Broadcast Mode.
IEEE Trans. Computers, 1994

Conflict Resolution and Fault-Free Path Selection in Multicast-Connected Cube-Based Networks.
IEEE Trans. Computers, 1994

The Full-Cube Topology: Properties and Routing.
Inf. Sci., 1994

1993
A Fault-Tolerant Digital Artificial Neuron.
IEEE Des. Test Comput., 1993

1992
A Simulation Analysis of Faults and Conflicts in a Multicast-Connected Multi-Path Cube-Based Network.
Proceedings of the 12th International Conference on Distributed Computing Systems, 1992

1991
C2SC: A Four-Path Fault Tolerant Interconnection Network.
Proceedings of the International Conference on Parallel Processing, 1991

1990
A parallel unification machine.
IEEE Micro, 1990

Parallel Unification Machine Design and Simulation.
Proceedings of the Parallelization in Inference Systems, 1990

Parallel Unification: Theory and Implementations.
Proceedings of the Parallelization in Inference Systems, 1990

1989
Design and performance measurements of a parallel machine for the unification algorithm.
Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989

A parallel unification coprocessor.
Proceedings of the IEEE International Workshop on Tools for Artificial Intelligence: Architectures, 1989


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