Adil Sarwar
Orcid: 0000-0002-8614-6697Affiliations:
- Aligarh Muslim University, Uttar Pradesh, India
According to our database1,
Adil Sarwar
authored at least 28 papers
between 2014 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
Performance evaluation of five-level packed U-cell inverter and its fault-tolerant variants.
Int. J. Circuit Theory Appl., February, 2024
2023
A nine-level common ground multilevel inverter (9L-CGMLI) with reduced components and boosting ability.
Int. J. Circuit Theory Appl., August, 2023
Novel Integrated NLC-SHE Control Applied in Cascaded Nine-Level H-Bridge Multilevel Inverter and Its Experimental Validation.
IEEE Access, 2023
A Single-Source Switched-Capacitor 13-Level High Gain Inverter With Lower Switch Stress.
IEEE Access, 2023
A Low Switch Count 13-Level Switched-Capacitor Inverter With Hexad Voltage-Boosting for Renewable Energy Integration.
IEEE Access, 2023
2022
A triple boost 13-level switched-capacitor based multi-level inverter topology for solar PV applications.
Int. J. Circuit Theory Appl., December, 2022
A 13-, 11-, and 9-Level Boosted Operation of a Single-Source Asymmetrical Inverter With Hybrid PWM Scheme.
IEEE Trans. Ind. Electron., 2022
An MPPT method using hybrid radial movement optimization with teaching-learning based optimization under fluctuating atmospheric conditions.
J. Intell. Fuzzy Syst., 2022
A novel voltage boosting switched-capacitor 19-level inverter with reduced component count.
Int. J. Circuit Theory Appl., 2022
Operation, analysis, and implementation of a reduced device count asymmetrical multilevel inverter.
Int. J. Circuit Theory Appl., 2022
Design and investigation of a triple boost multilevel inverter with self-balanced switched capacitors and reduced voltage stress.
Int. J. Circuit Theory Appl., 2022
2021
Int. J. Circuit Theory Appl., 2021
A twice boost nine-level switched-capacitor multilevel (2B-9L-SCMLI) inverter with self-voltage balancing capability.
Int. J. Circuit Theory Appl., 2021
A high gain noninverting DC-DC converter with low voltage stress for industrial applications.
Int. J. Circuit Theory Appl., 2021
Hardware-in-the-Loop Implementation of Projectile Target Search Algorithm for Selective Harmonic Elimination in a 3-Phase Multilevel Converter.
IEEE Access, 2021
Implementation of a Novel Variable Structure Nearest Level Modulation on Cascaded H-Bridge Multilevel Inverter.
IEEE Access, 2021
A Hybrid Nearest Level Combined With PWM Control Strategy: Analysis and Implementation on Cascaded H-Bridge Multilevel Inverter and its Fault Tolerant Topology.
IEEE Access, 2021
Rapid and Robust Adaptive Jaya (Ajaya) Based Maximum Power Point Tracking of a PV-Based Generation System.
IEEE Access, 2021
IEEE Access, 2021
IEEE Access, 2021
A Non-Pulsating Input Current Step-Up DC/DC Converter With Common Ground Structure for Photovoltaic Applications.
IEEE Access, 2021
M-Type and CD-Type Carrier Based PWM Methods and Bat Algorithm-Based SHE and SHM for Compact Nine-Level Switched Capacitor Inverter.
IEEE Access, 2021
IEEE Access, 2021
Implementation and Analysis of a 15-Level Inverter Topology With Reduced Switch Count.
IEEE Access, 2021
Performance Analysis and Hardware-in-the-Loop (HIL) Validation of Single Switch High Voltage Gain DC-DC Converters for MPP Tracking in Solar PV System.
IEEE Access, 2021
2019
Low Switching Frequency Based Asymmetrical Multilevel Inverter Topology With Reduced Switch Count.
IEEE Access, 2019
2014
IEEE Trans. Instrum. Meas., 2014