Zeeshan Sarwer

According to our database, Zeeshan Sarwer authored at least 7 papers between 2021 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

A nine-level common ground multilevel inverter (9L-CGMLI) with reduced components and boosting ability.

Zeeshan Sarwer, Md Nishat Anwar, Adil Sarwar

Int. J. Circuit Theory Appl., August, 2023

2022

Operation, analysis, and implementation of a reduced device count asymmetrical multilevel inverter.

Zeeshan Sarwer, Ankush Kumar Sharma, Mohammad Zaid, Adil Sarwar

Int. J. Circuit Theory Appl., 2022

Design and investigation of a triple boost multilevel inverter with self-balanced switched capacitors and reduced voltage stress.

Zeeshan Sarwer, Md Nishat Anwar, Adil Sarwar

Int. J. Circuit Theory Appl., 2022

A non-isolated quasi-Z-source-based high-gain DC-DC converter.

Arshad Mahmood, Mohammad Zaid, Shahrukh Khan, Marif Daula Siddique, Atif Iqbal, Zeeshan Sarwer

Int. J. Circuit Theory Appl., 2022

2021

Asymmetrical multilevel inverter topology with low total standing voltage and reduced switches count.

M. Saad Bin Arif, Zeeshan Sarwer, Marif Daula Siddique, Shahrin Bin Md. Ayob, Atif Iqbal, Saad Mekhilef

Int. J. Circuit Theory Appl., 2021

Implementation of a Novel Variable Structure Nearest Level Modulation on Cascaded H-Bridge Multilevel Inverter.

Zeeshan Sarwer, Adil Sarwar, Mohammad Zaid, Md. Reyaz Hussan, Mohd Tariq, Basem Alamri, Ahmad Aziz Alahmadi

IEEE Access, 2021

A Single Input Dual Output High Gain DC-DC Converter With Reduced Voltage Stress.

Shahrukh Khan, Kush Varshney, Mohammad Zaid, Mohd Tariq, Javed Ahmad, Zeeshan Sarwer

Proceedings of the IECON 2021, 2021