Adiwena Putra

Orcid: 0000-0001-6963-566X

According to our database1, Adiwena Putra authored at least 6 papers between 2021 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
23.10 HuMoniX: A 57.3fps 12.8TFLOPS/W Text-to-Motion Processor with Inter-Iteration Output Sparsity and Inter-Frame Joint Similarity.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

EXION: Exploiting Inter-and Intra-Iteration Output Sparsity for Diffusion Models.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

ABC-FHE: A Resource-Efficient Accelerator Enabling Bootstrappable Parameters for Client-Side Fully Homomorphic Encryption.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024
Morphling: A Throughput-Maximized TFHE-based Accelerator using Transform-domain Reuse.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

2021
Low Latency YOLOv3-Tiny Accelerator for Low-Cost FPGA Using General Matrix Multiplication Principle.
IEEE Access, 2021


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