Adiwena Putra
Orcid: 0000-0001-6963-566X
According to our database1,
Adiwena Putra authored at least 8 papers
between 2021 and 2026.
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Bibliography
2026
A 57.3-fps 12.8 TFLOPS/W Text-to-Motion Processor With Inter-Iteration Output Sparsity and Inter-Frame Joint Similarity.
IEEE J. Solid State Circuits, June, 2026
OmniCrypt: A 435.86M-GOPS/W Bootstrappable Multi-Scheme FHE Accelerator with on-Chip Data Generation for Privacy-Preserving Computation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
23.10 HuMoniX: A 57.3fps 12.8TFLOPS/W Text-to-Motion Processor with Inter-Iteration Output Sparsity and Inter-Frame Joint Similarity.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025
ABC-FHE: A Resource-Efficient Accelerator Enabling Bootstrappable Parameters for Client-Side Fully Homomorphic Encryption.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025
2024
Morphling: A Throughput-Maximized TFHE-based Accelerator using Transform-domain Reuse.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
2023
Strix: An End-to-End Streaming Architecture with Two-Level Ciphertext Batching for Fully Homomorphic Encryption with Programmable Bootstrapping.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
2021
Low Latency YOLOv3-Tiny Accelerator for Low-Cost FPGA Using General Matrix Multiplication Principle.
IEEE Access, 2021