Ahmed Shalash

According to our database, Ahmed Shalash authored at least 4 papers between 2016 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

A Cost-Effective Dynamic Partial Reconfiguration Implementation Flow for Xilinx FPGA.

Ahmed Kamaleldin, Islam Ahmed, Abdulfattah Mohammad Obeid, Ahmed Shalash, Yehea Ismail, Hassan Mostafa

Proceedings of the New Generation of CAS, 2017

A reconfigurable hardware platform implementation for software defined radio using dynamic partial reconfiguration on Xilinx Zynq FPGA.

Ahmed Kamaleldin, Sherif Hosny, Khaled Mohamed, Mostafa Gamal, Abdelrhman Hussien, Eslam Elnader, Ahmed Shalash, Abdelfattah Mohammad Obeid, Yehea Ismail, Hassan Mostafa

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Design guidelines for the high-speed dynamic partial reconfiguration based software defined radio implementations on Xilinx Zynq FPGA.

Ahmed Kamaleldin, Ahmed M. Soliman, Ahmed Nagy, Youssef Gamal, Ahmed Shalash, Yehea Ismail, Hassan Mostafa

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

A proposed methodology for designing reconfigurable solutions.

Abdulfattah Mohammad Obeid, Mohammed S. BenSaleh, Mohamed I. Alkanhal, Ahmed Shalash, Mohamed Abid

Proceedings of the 11th International Design & Test Symposium, 2016