Yehea I. Ismail
According to our database^{1},
Yehea I. Ismail
authored at least 239 papers
between 1998 and 2020.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2011, "For contributions to highperformance circuits and interconnects".
Timeline
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Online presence:

on aucegypt.edu
On csauthors.net:
Bibliography
2020
Multibit error control coding with limited correction for highperformance and energyefficient network on chip.
IET Circuits Devices Syst., 2020
2019
Microelectron. J., 2019
Integr., 2019
Microelectrodes based on CMOS Technology for Charactrization of Biological Cells.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2019
Planar Microelectrodes versus Cone Plate for Biological Cell Trapping and Charcterization.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2019
Proceedings of the 31st International Conference on Microelectronics, 2019
Proceedings of the 31st International Conference on Microelectronics, 2019
A novel microfluidic system using a reservoir and flow control system for singlecell release, migration, separation, and characterization.
Proceedings of the 31st International Conference on Microelectronics, 2019
Optimization of microelectrodes for DNA fragments labelled to microbeads manipulation and characterization.
Proceedings of the 31st International Conference on Microelectronics, 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A Low Power Selfhealing Resilient Microarchitecture for PVT Variability Mitigation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 93% Peak Efficiency FullyIntegrated Multilevel Multistate Hybrid DCDC Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Microelectron. J., 2018
A LowPower HighEfficiency Inductive Link Power Supply for Neural Recording and Stimulation SystemonChip.
J. Low Power Electron., 2018
Technology Scaling Roadmap for FinFETBased FPGA Clusters Under Process Variations.
J. Circuits Syst. Comput., 2018
Integr., 2018
Twodimensional models for quantum effects on short channel electrostatics of lightly doped symmetric doublegate MOSFETs.
IET Circuits Devices Syst., 2018
IEEE Access, 2018
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Fully Integrated Mixed Mode Interface Circuit in 65 nm CMOS for Leukemia Detection and Classification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 30th International Conference on Microelectronics, 2018
ASIC Implementation of EnergyOptimized Successive Cancellation Polar Decoders for Internet of Things.
Proceedings of the 30th International Conference on Microelectronics, 2018
Proceedings of the IEEE 8th Annual Computing and Communication Workshop and Conference, 2018
2017
PASSIOT: A Paretooptimal multiobjective optimization approach for synthesis of analog circuits using Sobol' indicesbased engine.
Integr., 2017
Towards the implementation of Multiband Multistandard SoftwareDefined Radio using Dynamic Partial Reconfiguration.
Int. J. Commun. Syst., 2017
Accurate ClosedForm Expressions for the Bit RateWireless Transmission Distance Relationship in IRUWBoF Systems.
IEEE Commun. Lett., 2017
A CostEffective Dynamic Partial Reconfiguration Implementation Flow for Xilinx FPGA.
Proceedings of the New Generation of CAS, 2017
Proceedings of the New Generation of CAS, 2017
Proceedings of the New Generation of CAS, 2017
Proceedings of the New Generation of CAS, 2017
Characterization and model validation of triboelectric nanogenerators using VerilogA.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
A reconfigurable hardware platform implementation for software defined radio using dynamic partial reconfiguration on Xilinx Zynq FPGA.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
A 1 GS/s 6bit timebased analogtodigital converter (TADC) for frontend receivers.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Dielectric analysis of changes in electric properties of leukemic cells through travelling and negative dielectrophoresis with 2D electrodes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Design guidelines for the highspeed dynamic partial reconfiguration based software defined radio implementations on Xilinx Zynq FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Lowpower highaccuracy seizure detection algorithms for neural implantable platforms.
Proceedings of the 29th International Conference on Microelectronics, 2017
Design of a timebased capacitancetodigital converter using current starved inverters.
Proceedings of the 29th International Conference on Microelectronics, 2017
An improved design for high speed analog applications of the fully differential operational floating conveyor.
Proceedings of the 29th International Conference on Microelectronics, 2017
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017
Proceedings of the IEEE 7th Annual Computing and Communication Workshop and Conference, 2017
A Model of Electrokinetic Platform for Separation of Different Sizes of Biological Particles.
Proceedings of the International Conference on Advanced Intelligent Systems and Informatics 2017, 2017
2016
Adaptive Multibit CrosstalkAware Error Control Coding Scheme for OnChip Communication.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
ERSUT: A SelfHealing Architecture for Mitigating PVT Variations Without Pipeline Flushing.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A 2D compact model for lightly doped DG MOSFETs (PDGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs).
Microelectron. Reliab., 2016
Statistical yield improvement under process variations of multivalued memristorbased memories.
Microelectron. J., 2016
Microelectron. J., 2016
On the use of a programmable frontend for multiband/multistandard applications.
Microelectron. J., 2016
A 200 MS/s 8bit Timebased AnalogtoDigital Converter with inherit sample and hold.
Proceedings of the 29th IEEE International SystemonChip Conference, 2016
A 130 nm CMOS integrated LabOnaChip based on DeFET sensor for biomedical analysis.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Design of low power CMOS subthreshold current mode instrumentation amplifier based on CCII.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Accuracyimproved coupling capacitance model for throughsilicon via (TSV) arrays using dimensional analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
TCGSP: An improved floorplan representation based on an efficient hybrid of Transitive Closure Graph and Sequence Pair.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 11th International Design & Test Symposium, 2016
Leakage power evaluation of FinFETbased FPGA cluster under threshold voltage variation.
Proceedings of the 11th International Design & Test Symposium, 2016
Proceedings of the 28th International Conference on Microelectronics, 2016
Proceedings of the 28th International Conference on Microelectronics, 2016
ASICoriented comparative review of hardware security algorithms for internet of things applications.
Proceedings of the 28th International Conference on Microelectronics, 2016
Presenting a synchronous  Asynchronous standard cell library based on 7nm FinFET technology.
Proceedings of the 28th International Conference on Microelectronics, 2016
Proceedings of the 28th International Conference on Microelectronics, 2016
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016
2015
A 76.8 MHz temperature compensated MEMS reference oscillator for wireless handsets.
Microelectron. J., 2015
Microscale variationtolerant exponential tracking energy harvesting system for wireless sensor networks.
Microelectron. J., 2015
Library based macromodeling methodology for Through Silicon Via (TSV) arbitrary arrays.
Microelectron. J., 2015
Lab on a Chip Based on CMOS Technology: System Architectures, Microfluidic Packaging, and Challenges.
IEEE Des. Test, 2015
New TSVBased applications: Resonant inductive coupling, variable inductor, power amplifier, bandpass filter, and antenna.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Performance evaluation of FinFETbased FPGA cluster under threshold voltage variation.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Deadlock detection in conditional asynchronous circuits under mismatched branch selection.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
A comparative evaluation of singlewalled carbon nanotubes and copper in interconnects and ThroughSilicon Vias.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Tutorial 1: Labonachip based on CMOS technology: Parts, applications, challenges and future trends.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
A simple hybrid 3level buckboost DCDC converter with efficient PWM regulation scheme.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
A 24 Gbps SerDes transceiver for onchip networks using a new halfdatarate selftimed 3level signaling scheme.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015
A new digital current sensing technique suitable for low power energy harvesting systems.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015
Different scenarios for estimating coupling capacitances of through silicon via (TSV) arrays.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015
5Level buck converter with reduced inductor size suitable for onchip integration.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015
A tunable receiver architecture utilizing timevarying matching network for a universal receiver.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015
2014
CrosstalkAware Multiple Error Detection Scheme Based on TwoDimensional Parities for Energy Efficient Network on Chip.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A variation tolerant driving technique for alldigital selftimed 3level signaling highspeed SerDes transceivers for onchip networks.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A novel dimensional analysis method for TSV modeling and analysis in three dimensional integrated circuits.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Lowpower alldigital manchesterencodingbased highspeed serdes transceiver for onchip networks.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 26th International Conference on Microelectronics, 2014
Proceedings of the 26th International Conference on Microelectronics, 2014
A design oriented model for timing jitter/skew of VoltagetoTime Converter (VTC) circuits.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014
Circuit design techniques for increasing the output power of switched capacitor charge pumps.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Highlylinear voltagetotime converter (VTC) circuit for timebased analogtodigital converters (TADCs).
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Microscale Solar Energy Harvesting for Wireless Sensor Networks based on Exponential Maximum power locking technique.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Proceedings of the 20th IEEE International Conference on Electronics, 2013
New hybrid battery model that takes into account both electric circuit characteristics and nonlinear battery properties.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Proceedings of Eurocon 2013, 2013
Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using ModelBased Simulation.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013
2012
Synthesizable delay line architectures for digitally controlled voltage regulators.
Proceedings of the IEEE 25th International SOC Conference, 2012
Proceedings of the IEEE 25th International SOC Conference, 2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A 510GHz low power bangbang all digital PLL based on programmable digital loop filter.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Modeling and analysis of through silicon via: Electromagnetic and device simulation approach.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Effect of nonuniform substrate doping profile on the electrical performance of throughsiliconvia for low power application.
Proceedings of the International Conference on Energy Aware Computing, 2012
Proceedings of the International Conference on Energy Aware Computing, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
FASTAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Microelectron. J., 2011
Fast hysteretic control of onchip multiphase switchedcapacitor dcdc converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 6th IEEE International Design and Test Workshop, 2011
Proceedings of the International Conference on Energy Aware Computing, 2011
Slowswitchinglimit loss removal in SC DCDC converters using adiabatic charging.
Proceedings of the International Conference on Energy Aware Computing, 2011
Proceedings of the International Conference on Energy Aware Computing, 2011
A design methodology for a low power bangbang all digital PLL based on digital loop filter programmable coefficients.
Proceedings of the International Conference on Energy Aware Computing, 2011
Proceedings of the International Conference on Energy Aware Computing, 2011
Equivalent lumped element models for various nport Through Silicon Vias networks.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
SACTA: A SelfAdjusting Clock Tree Architecture for Adapting to ThermalInduced Delay Variation.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Stable Parallelizable Model Order Reduction for Circuits With FrequencyDependent Elements.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Microelectron. J., 2009
2008
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Area Optimization for Leakage Reduction and Thermal Stability in NanometerScale Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Accurate analytical delay modeling of CMOS clock buffers considering power supply variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 1st international forum on Nextgeneration multicore/manycore technologies, 2008
2007
VariationTolerant and LowPower SourceSynchronous Multicycle OnChip Interconnect Scheme.
VLSI Design, 2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
J. Circuits Syst. Comput., 2007
Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, 2007
Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 2007 International Conference on ComputerAided Design, 2007
Proceedings of the 2007 International Conference on ComputerAided Design, 2007
Proceedings of the 2007 International Conference on ComputerAided Design, 2007
NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
Proceedings of the 2006 International Conference on ComputerAided Design, 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Computation of accurate interconnect process parameter values for performance corners under process variations.
Proceedings of the 43rd Design Automation Conference, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Realizable reduction of interconnect circuits including self and mutual inductances.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Skewing adjacent line repeaters to reduce the delay and energy dissipation of onchip buses.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A Skewed Repeater Bus Architecture for OnChip Energy Reduction in Microprocessors.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 2005 International Conference on ComputerAided Design, 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Engineering OverClocking: ReliabilityPerformance TradeOffs for HighPerformance Register Files.
Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 42nd Design Automation Conference, 2005
The importance of including thermal effects in estimating the effectiveness of power reduction techniques.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Modeling skin and proximity effects with reduced realizable RL circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2004
Utilizing the effect of relative delay on energy dissipation in lowpower onchip buses.
IEEE Trans. Very Large Scale Integr. Syst., 2004
Computation of signalthreshold crossing times directly from higher order moments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Proceedings of the 4th IEEE International Workshop on SystemonChip for RealTime Applications (IWSOC'04), 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Effect of relative delay on the dissipated energy in coupled interconnects.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Low power couplingbased encoding for onchip buses.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 International Conference on ComputerAided Design, 2004
Proceedings of the 2004 International Conference on ComputerAided Design, 2004
Analysis of coupling noise and it's scalability in dynamic circuits [dynamic logic CMOS ICs].
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
J. Circuits Syst. Comput., 2003
Proceedings of the 3rd IEEE International Workshop on SystemonChip for RealTime Applications (IWSOC'03), 30 June, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 40th Design Automation Conference, 2003
2002
Guest editorial: special issue on onchip inductance in highspeed integrated circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
DTT: direct truncation of the transfer function  an alternative tomoment matching for tree structured interconnect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
J. Circuits Syst. Comput., 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computeraided Design, 2002
2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
2000
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 IEEE/ACM International Conference on ComputerAided Design, 1999
Proceedings of the 36th Conference on Design Automation, 1999
1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Dynamic and ShortCircuit Power of CMOS Gates Driving Lossless Transmission Lines.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLSVLSI '98), 1998