Yehea I. Ismail

According to our database1, Yehea I. Ismail authored at least 239 papers between 1998 and 2020.

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Awards

IEEE Fellow

IEEE Fellow 2011, "For contributions to high-performance circuits and interconnects".

Timeline

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Bibliography

2020
Multi-bit error control coding with limited correction for high-performance and energy-efficient network on chip.
IET Circuits Devices Syst., 2020

2019
Power adaptive high-resolution neural data compression algorithm (PANDCA).
Microelectron. J., 2019

An accurate model of domain-wall-based spintronic memristor.
Integr., 2019

Micro-electrodes based on CMOS Technology for Charactrization of Biological Cells.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2019

Planar Micro-electrodes versus Cone Plate for Biological Cell Trapping and Charcterization.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2019

Microfluidic Platform for Monitoring the Dielectric Parameters of U2OS Cells.
Proceedings of the 31st International Conference on Microelectronics, 2019

Modeling of Double-gate LDMOSFET Devices including Self-heating.
Proceedings of the 31st International Conference on Microelectronics, 2019

A novel microfluidic system using a reservoir and flow control system for single-cell release, migration, separation, and characterization.
Proceedings of the 31st International Conference on Microelectronics, 2019

Optimization of micro-electrodes for DNA fragments labelled to microbeads manipulation and characterization.
Proceedings of the 31st International Conference on Microelectronics, 2019

2018
A 0.4-V Miniature CMOS Current Mode Instrumentation Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 93% Peak Efficiency Fully-Integrated Multilevel Multistate Hybrid DC-DC Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Dual Split-Merge: A high throughput router architecture for FPGAs.
Microelectron. J., 2018

A Low-Power High-Efficiency Inductive Link Power Supply for Neural Recording and Stimulation System-on-Chip.
J. Low Power Electron., 2018

Technology Scaling Roadmap for FinFET-Based FPGA Clusters Under Process Variations.
J. Circuits Syst. Comput., 2018

Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources.
Integr., 2018

Two-dimensional models for quantum effects on short channel electrostatics of lightly doped symmetric double-gate MOSFETs.
IET Circuits Devices Syst., 2018

Thermal Resistance Model for Standard CMOS Thermoelectric Generator.
IEEE Access, 2018

Security Analysis of Chaotic Baker Maps.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

Electroporation Improvement of Leukemic Cells Using Dielectrophoresis Technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Fully Integrated Mixed Mode Interface Circuit in 65 nm CMOS for Leukemia Detection and Classification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

HEVC Implementation for IoT Applications.
Proceedings of the 30th International Conference on Microelectronics, 2018

ASIC Implementation of Energy-Optimized Successive Cancellation Polar Decoders for Internet of Things.
Proceedings of the 30th International Conference on Microelectronics, 2018

Internet of things: A comparative study.
Proceedings of the IEEE 8th Annual Computing and Communication Workshop and Conference, 2018

2017
PASSIOT: A Pareto-optimal multi-objective optimization approach for synthesis of analog circuits using Sobol' indices-based engine.
Integr., 2017

Towards the implementation of Multi-band Multi-standard Software-Defined Radio using Dynamic Partial Reconfiguration.
Int. J. Commun. Syst., 2017

Accurate Closed-Form Expressions for the Bit Rate-Wireless Transmission Distance Relationship in IR-UWBoF Systems.
IEEE Commun. Lett., 2017

A Cost-Effective Dynamic Partial Reconfiguration Implementation Flow for Xilinx FPGA.
Proceedings of the New Generation of CAS, 2017

Exploiting the Dynamic Partial Reconfiguration on NoC-Based FPGA.
Proceedings of the New Generation of CAS, 2017

A Low-Power Self-Startup Bandgap Circuit for Energy Efficient Applications.
Proceedings of the New Generation of CAS, 2017

The Impact of Soft Errors on Memristor-Based Memory.
Proceedings of the New Generation of CAS, 2017

Characterization and model validation of triboelectric nanogenerators using Verilog-A.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Area-efficient read/write circuit for spintronic memristor based memories.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A reconfigurable hardware platform implementation for software defined radio using dynamic partial reconfiguration on Xilinx Zynq FPGA.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A 1 GS/s 6-bit time-based analog-to-digital converter (T-ADC) for front-end receivers.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A VCO-Based MPPT Circuit for Low-Voltage Energy Harvesters.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A Novel CMOS-Based Fully Differential Operational Floating Conveyor.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

3D-NOCET: A tool for implementing 3D-NoCs based on the Direct-Elevator algorithm.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Dielectric analysis of changes in electric properties of leukemic cells through travelling and negative dielectrophoresis with 2-D electrodes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Design guidelines for the high-speed dynamic partial reconfiguration based software defined radio implementations on Xilinx Zynq FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

130nm Low power asynchronous AES core.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Power efficient AES core for IoT constrained devices implemented in 130nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Low-power high-accuracy seizure detection algorithms for neural implantable platforms.
Proceedings of the 29th International Conference on Microelectronics, 2017

Design of a time-based capacitance-to-digital converter using current starved inverters.
Proceedings of the 29th International Conference on Microelectronics, 2017

An improved design for high speed analog applications of the fully differential operational floating conveyor.
Proceedings of the 29th International Conference on Microelectronics, 2017

Wideband inductorless CMOS RF front-end for LTE receivers.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

Clock signal characterization for signal integrity.
Proceedings of the IEEE 7th Annual Computing and Communication Workshop and Conference, 2017

A Model of Electrokinetic Platform for Separation of Different Sizes of Biological Particles.
Proceedings of the International Conference on Advanced Intelligent Systems and Informatics 2017, 2017

2016
Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

ERSUT: A Self-Healing Architecture for Mitigating PVT Variations Without Pipeline Flushing.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 2D compact model for lightly doped DG MOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs).
Microelectron. Reliab., 2016

Statistical yield improvement under process variations of multi-valued memristor-based memories.
Microelectron. J., 2016

Electronic frequency compensation of AlN-on-Si MEMS reference oscillators.
Microelectron. J., 2016

On the use of a programmable front-end for multi-band/multi-standard applications.
Microelectron. J., 2016

A 200 MS/s 8-bit Time-based Analog-to-Digital Converter with inherit sample and hold.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

A 130 nm CMOS integrated Lab-On-a-Chip based on DeFET sensor for biomedical analysis.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Design of low power CMOS subthreshold current mode instrumentation amplifier based on CCII.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

A 3D model of quadrupole dielectrophoresis levitation.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Design guidelines for embeded NoCs on FPGAs.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Accuracy-improved coupling capacitance model for through-silicon via (TSV) arrays using dimensional analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

TCG-SP: An improved floorplan representation based on an efficient hybrid of Transitive Closure Graph and Sequence Pair.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Five-level hybrid DC-DC converter with enhanced light-load efficiency.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Evaluation of multi-level buck converters for low-power applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

RC-In-RC-Out model order reduction via node merging.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Design guidelines for soft implementations to embedded NoCs of FPGAs.
Proceedings of the 11th International Design & Test Symposium, 2016

Leakage power evaluation of FinFET-based FPGA cluster under threshold voltage variation.
Proceedings of the 11th International Design & Test Symposium, 2016

A Lab-On-a-Chip front-end based on DeFET sensor array for biomedical analysis.
Proceedings of the 28th International Conference on Microelectronics, 2016

A voltage multiplying AC/DC converter for energy harvesting applications.
Proceedings of the 28th International Conference on Microelectronics, 2016

ASIC-oriented comparative review of hardware security algorithms for internet of things applications.
Proceedings of the 28th International Conference on Microelectronics, 2016

Presenting a synchronous - Asynchronous standard cell library based on 7nm FinFET technology.
Proceedings of the 28th International Conference on Microelectronics, 2016

A 2D model of different electrode shapes for traveling wave dielectrophoresis.
Proceedings of the 28th International Conference on Microelectronics, 2016

A 0.4V 90nm CMOS subthreshold current conveyor.
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

2015
A 76.8 MHz temperature compensated MEMS reference oscillator for wireless handsets.
Microelectron. J., 2015

Micro-scale variation-tolerant exponential tracking energy harvesting system for wireless sensor networks.
Microelectron. J., 2015

Library based macro-modeling methodology for Through Silicon Via (TSV) arbitrary arrays.
Microelectron. J., 2015

Lab on a Chip Based on CMOS Technology: System Architectures, Microfluidic Packaging, and Challenges.
IEEE Des. Test, 2015

New TSV-Based applications: Resonant inductive coupling, variable inductor, power amplifier, bandpass filter, and antenna.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

A new digital locking MPPT control for ultra low power energy harvesting systems.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Performance evaluation of FinFET-based FPGA cluster under threshold voltage variation.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Design of adiabatic TSV, SWCNT TSV, and Air-Gap Coaxial TSV.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Analysis and optimization for dynamic read stability in 28nm SRAM bitcells.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A tunable multi-band/multi-standard receiver front-end supporting LTE.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Deadlock detection in conditional asynchronous circuits under mismatched branch selection.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A comparative evaluation of single-walled carbon nanotubes and copper in interconnects and Through-Silicon Vias.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Coupling capacitance extraction in through-silicon via (TSV) arrays.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Performance evaluation of wavelength exchanging in optical interconnect.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Tutorial 1: Lab-on-a-chip based on CMOS technology: Parts, applications, challenges and future trends.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A CMOS based operational floating current conveyor and its applications.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A CMOS based operational floating current conveyor.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A simple hybrid 3-level buck-boost DC-DC converter with efficient PWM regulation scheme.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015

VHDL implementation of a power management algorithm for PV-battery system.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015

Dual output power management unit for a PV-battery hybrid energy system.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015

A new digital current sensing technique suitable for low power energy harvesting systems.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015

Different scenarios for estimating coupling capacitances of through silicon via (TSV) arrays.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015

5-Level buck converter with reduced inductor size suitable for on-chip integration.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015

A tunable receiver architecture utilizing time-varying matching network for a universal receiver.
Proceedings of the 5th International Conference on Energy Aware Computing Systems & Applications, 2015

2014
Crosstalk-Aware Multiple Error Detection Scheme Based on Two-Dimensional Parities for Energy Efficient Network on Chip.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A novel dimensional analysis method for TSV modeling and analysis in three dimensional integrated circuits.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Performance evaluation of finFET based SRAM under statistical VT variability.
Proceedings of the 26th International Conference on Microelectronics, 2014

A programmable receiver front-end architecture supporting LTE.
Proceedings of the 26th International Conference on Microelectronics, 2014

A design oriented model for timing jitter/skew of Voltage-to-Time Converter (VTC) circuits.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

Circuit design techniques for increasing the output power of switched capacitor charge pumps.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

2013
Editorial Appointments for the 2013-2014 Term.
IEEE Trans. Very Large Scale Integr. Syst., 2013

TSV-based on-chip inductive coupling communications.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

VHDL implementation of Maximum Power Point Tracking algorithms.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Highly-linear voltage-to-time converter (VTC) circuit for time-based analog-to-digital converters (T-ADCs).
Proceedings of the 20th IEEE International Conference on Electronics, 2013

TPQA: Three point quadrature approximation MPPT algorithm.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Microscale Solar Energy Harvesting for Wireless Sensor Networks based on Exponential Maximum power locking technique.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Variability mitigation using correction function technique.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

New hybrid battery model that takes into account both electric circuit characteristics and non-linear battery properties.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

A macro-modeling approach for through silicon via.
Proceedings of Eurocon 2013, 2013

Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

2012
Synthesizable delay line architectures for digitally controlled voltage regulators.
Proceedings of the IEEE 25th International SOC Conference, 2012

A novel digital loop filter architecture for bang-bang ADPLL.
Proceedings of the IEEE 25th International SOC Conference, 2012

Emitter-coupled spin-transistor logic.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Switched-capacitor dc-dc converters with output inductive filter.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A closed form expression for TSV-based on-chip spiral inductor.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A 16Gbps low power self-timed SerDes transceiver for multi-core communication.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Modeling and analysis of through silicon via: Electromagnetic and device simulation approach.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Effect of non-uniform substrate doping profile on the electrical performance of through-silicon-via for low power application.
Proceedings of the International Conference on Energy Aware Computing, 2012

Design methodology for square wave resonant clock generators.
Proceedings of the International Conference on Energy Aware Computing, 2012

InMnAs magnetoresistive spin-diode logic.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Modeling the response of Bang-Bang digital PLLs to phase error perturbations.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Editorial.
IEEE Trans. Very Large Scale Integr. Syst., 2011

FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Novel Moment Based Framework for Accurate and Efficient Static Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Floorplanning for low power IC design considering temperature variations.
Microelectron. J., 2011

Fast hysteretic control of on-chip multi-phase switched-capacitor dc-dc converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Compact lumped element model for TSV in 3D-ICs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 12Gbps all digital low power SerDes transceiver for on-chip networking.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A dynamic calibration scheme for on-chip process and temperature variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A Comprehensive Tapered buffer optimization algorithm for unified design metrics.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Body contact based TSV equalizer.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Resonant square-wave clock generator for low power applications.
Proceedings of the International Conference on Energy Aware Computing, 2011

Slow-switching-limit loss removal in SC DC-DC converters using adiabatic charging.
Proceedings of the International Conference on Energy Aware Computing, 2011

All-digital comparator using device-ratio programmable triggering levels.
Proceedings of the International Conference on Energy Aware Computing, 2011

A design methodology for a low power bang-bang all digital PLL based on digital loop filter programmable coefficients.
Proceedings of the International Conference on Energy Aware Computing, 2011

Low power FPAA design based on OTA using 90nm CMOS technology.
Proceedings of the International Conference on Energy Aware Computing, 2011

Equivalent lumped element models for various n-port Through Silicon Vias networks.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A novel variation insensitive clock distribution methodology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
A Timing-Dependent Power Estimation Framework Considering Coupling.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Stable Parallelizable Model Order Reduction for Circuits With Frequency-Dependent Elements.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Serial-Link Bus: A Low-Power On-Chip Bus Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Guest Editorial Special Issue on ISCAS 2008.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

SRAM dynamic stability estimation using MPFP and its applications.
Microelectron. J., 2009

2008
Inductance Effects in Global Nets.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Accurate Estimation of SRAM Dynamic Stability.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Analytical Model for the Propagation Delay of Through Silicon Vias.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Accurate analytical delay modeling of CMOS clock buffers considering power supply variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Power-supply-variation-aware timing analysis of synchronous systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Interconnect design and limitations in nanoscale technologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A global interconnect link design for many-core microprocessors.
Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, 2008

2007
Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme.
VLSI Design, 2007

Thermal Management of On-Chip Caches Through Power Density Minimization.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2007

On the Scaling of Temperature-Dependent Effects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

An Accurate Low-Iteration Algorithm for Effective Capacitance Computation.
J. Circuits Syst. Comput., 2007

Variable latency caches for nanoscale processor.
Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, 2007

Modeling and Characterizing Power Variability in Multicore Architectures.
Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007

Variable Threshold Voltage Design Scheme for CMOS Tapered Buffers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Compact and Accurate Temperature-Dependent Model for CMOS Circuit Delay.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Attaining Thermal Integrity in Nanometer Chips.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Approximate Frequency Response Models for RLC Power Grids.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Including inductance in static timing analysis.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A self-adjusting clock tree architecture to cope with temperature variations.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Multi-layer interconnect performance corners for variation-aware timing analysis.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
Realistic scalability of noise in dynamic circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Formal derivation of optimal active shielding for low-power on-chip buses.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Reducing the Data Switching Activity on Serial Link Buses.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Optimum sizing of power grids for IR drop.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Reducing the data switching activity of serialized datastreams.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Importance of volume discretization of single and coupled interconnects.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Power density minimization for highly-associative caches in embedded processors.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Computation of accurate interconnect process parameter values for performance corners under process variations.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Optimum positioning of interleaved repeaters in bidirectional buses.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Weibull-based analytical waveform model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Realizable reduction of interconnect circuits including self and mutual inductances.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Accurate decoupling of capacitively coupled buses.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Expanding the frequency range of AWE via time shifting.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Physical limitations on the bit-rate of on-chip interconnects.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files.
Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005

Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd Design Automation Conference, 2005

Piece-wise approximations of RLCK circuit responses using moment matching.
Proceedings of the 42nd Design Automation Conference, 2005

The importance of including thermal effects in estimating the effectiveness of power reduction techniques.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Low-power prediction based data transfer architecture.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Modeling skin and proximity effects with reduced realizable RL circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Computation of signal-threshold crossing times directly from higher order moments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Low-power on-chip bus architecture using dynamic relative delays.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Possible Noise Failure Modes in Static and Dynamic Circuits.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Effect of relative delay on the dissipated energy in coupled interconnects.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Low power coupling-based encoding for on-chip buses.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Powder-based fabrication techniques for single-wall carbon nanotube circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Formal derivation of optimal active shielding for low-power on-chip buses.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Modeling unbuffered latches for timing analysis.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Analysis of coupling noise and it's scalability in dynamic circuits [dynamic logic CMOS ICs].
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Improved model-order reduction by using spacial information in moments.
IEEE Trans. Very Large Scale Integr. Syst., 2003

On the Extraction of On-Chip Inductance.
J. Circuits Syst. Comput., 2003

Analysis of Coupling Noise in Dynamic Circuit.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Modeling skin effect with reduced decoupled R-L circuits.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Accurate rise time and overshoots estimation in RLC interconnects.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Realizable reduction of RLC circuits using node elimination.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Efficient model order reduction including skin effect.
Proceedings of the 40th Design Automation Conference, 2003

Realizable RLCK circuit crunching.
Proceedings of the 40th Design Automation Conference, 2003

2002
Guest editorial: special issue on on-chip inductance in high-speed integrated circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2002

On-chip inductance cons and pros.
IEEE Trans. Very Large Scale Integr. Syst., 2002

DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Inductance Effects in RLC Trees.
J. Circuits Syst. Comput., 2002

Evaluating noise pulses in RC networks due to capacitive coupling.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Efficient model order reduction via multi-node moment matching.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001
Exploiting the on-chip inductance in high-speed clock distribution networks.
IEEE Trans. Very Large Scale Integr. Syst., 2001

2000
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Equivalent Elmore delay for RLC trees.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Sensitivity of interconnect delay to on-chip inductance.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Figures of merit to characterize the importance of on-chip inductance.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Signal waveform characterization in RLC trees.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Repeater insertion in RLC lines for minimum propagation delay.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Repeater insertion in tree structured inductive interconnect.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Equivalent Elmore Delay for <i>RLC</i> Trees.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Power dissipated by CMOS gates driving lossless transmission lines.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Transient power in CMOS gates driving LC transmission lines.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998


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