Ahmed Youssef

Affiliations:
  • Intel, Inc., Santa Clara, CA, USA
  • University of Waterloo, ON, Canada (PhD 2008)


According to our database1, Ahmed Youssef authored at least 7 papers between 2004 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2010
On the Power Management of Simultaneous Multithreading Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A Power-Efficient Multipin ILP-Based Routing Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2008
A Comparative Study Between Static and Dynamic Sleep Signal Generation Techniques for Leakage Tolerant Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2008

2007
A Low-Power Multi-Pin Maze Routing Methodology.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006
Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

2005
POMR: a power-aware interconnect optimization methodology.
IEEE Trans. Very Large Scale Integr. Syst., 2005

2004
POMR: a power-optimal maze routing methodology.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004


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