Mohamed I. Elmasry

Proceedings of the 12th International Conference on Information, 2021

2017

On the Fault Tolerance of Stochastic Decoders.

[BibT_eX]

[DOI]

Assem S. Hussein

Vincent C. Gaudet

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

2016

A 16-bit high-speed low-power hybrid adder.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Microelectronics, 2016

2013

Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Negative capacitance circuits for process variations compensation and timing yield improvement.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012

On-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB).

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

2011

A Bias-Dependent Model for the Impact of Process Variations on the SRAM Soft Error Immunity.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

A Novel Low Area Overhead Direct Adaptive Body Bias (D-ABB) Circuit for Die-to-Die and Within-Die Variations Compensation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Analytical Soft Error Models Accounting for Die-to-Die and Within-Die Variations in Sub-Threshold SRAM Cells.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Adaptive Body Bias for Reducing the Impacts of NBTI and Process Variations on 6T SRAM Cells.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Novel Timing Yield Improvement Circuits for High-Performance Low-Power Wide Fan-In Dynamic OR Gates.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010

On the Power Management of Simultaneous Multithreading Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

A Power-Efficient Multipin ILP-Based Routing Technique.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A Design-Oriented Soft Error Rate Variation Model Accounting for Both Die-to-Die and Within-Die Variations in Submicrometer CMOS SRAM Cells.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Discrete cooperative particle swarm optimization for FPGA placement.

[BibT_eX]

[DOI]

Appl. Soft Comput., 2010

Statistical timing yield improvement of dynamic circuits using negative capacitance technique.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Comparative analysis of power yield improvement under process variation of sub-threshold flip-flops.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Total Power Modeling in FPGAs Under Spatial Correlation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

A New Loss Compensation Technique for CMOS Distributed Amplifiers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

Comparative Analysis of Timing Yield Improvement under Process Variations of Flip-Flops Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2008

A Comparative Study Between Static and Dynamic Sleep Signal Generation Techniques for Leakage Tolerant Designs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

A Low-Noise CMOS Distributed Amplifier for Ultra-Wide-Band Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Analysis of the Flash ADC Bandwidth-Accuracy Tradeoff in Deep-Submicron CMOS Technologies.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Input Vector Reordering for Leakage Power Reduction in FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A 6-Bit 1.6-GS/sLow-Power Wideband Flash ADC Converter in 0.13-µm CMOS Technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

2007

A 10dB 44GHz Loss-Compensated CMOS Distributed Amplifier.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Low-Power Multi-Pin Maze Routing Methodology.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Lumped-element analysis and design of CMOS distributed amplifiers with image impedance termination.

[BibT_eX]

[DOI]

Microelectron. J., 2006

Low-power multi-threshold MCML: Analysis, design, and variability.

[BibT_eX]

[DOI]

Microelectron. J., 2006

Impact of technology scaling and process variations on RF CMOS devices.

[BibT_eX]

[DOI]

Microelectron. J., 2006

Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units.

[BibT_eX]

[DOI]

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

A novel loss compensation technique for broadband CMOS distributed amplifiers.

[BibT_eX]

[DOI]

Mohammad Ibrahim Elmasry

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A termination technique for the averaging network of flash ADC's.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 10-GHz 15-dB four-stage distributed amplifier in 0.18 µm CMOS process.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

POMR: a power-aware interconnect optimization methodology.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

MOS current mode circuits: analysis, design, and variability.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Memoryless Viterbi decoder.

[BibT_eX]

[DOI]

Dalia A. El-Dib

IEEE Trans. Circuits Syst. II Express Briefs, 2005

Design and optimization of MOS current mode logic for parameter variations.

[BibT_eX]

[DOI]

Integr., 2005

A Low-Power Partitioning Methodology by Maximizing Sleep Time and Minimizing Cut Nets.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

LAP: a logic activity packing methodology for leakage power-tolerant FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Activity Packing in FPGAs for Leakage Power Reduction.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

2004

Phase-domain fractional-N frequency synthesizers.

[BibT_eX]

[DOI]

Ayman ElSayed

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Modified register-exchange Viterbi decoder for low-power wireless communications.

[BibT_eX]

[DOI]

Dalia A. El-Dib

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

POMR: a power-optimal maze routing methodology.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Analog-to-digital conversion for SONET OC-192.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

MOS current mode logic: design, optimization, and variability.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Impact of technology scaling on RF CMOS.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Analysis and design of low-power multi-threshold MCML.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

A novel matrix-based lumped-element analysis method for CMOS distributed amplifiers.

[BibT_eX]

[DOI]

Mohammad Ibrahim Elmasry

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

A fast lock digital phase-locked-loop architecture for wireless applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

A wideband sigma-delta phase-locked-loop modulator for wireless applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

Design and optimization of multithreshold CMOS (MTCMOS) circuits.

[BibT_eX]

[DOI]

Shawki Areibi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2002

Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Low-power high-performance arithmetic circuits and architectures.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2002

A methodology for substrate crosstalk evaluation for system-on-a-chip.

[BibT_eX]

[DOI]

Integr. Comput. Aided Eng., 2002

Fractional-N frequency synthesizer for wireless communications.

[BibT_eX]

[DOI]

A. E. Hussein

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Low-power register-exchange Viterbi decoder for high-speed wireless communications.

[BibT_eX]

[DOI]

D. A. F. Ei-Dib

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Self-timed MOS current mode logic for digital applications.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A Novel Analytical Model for Evaluation of Substrate Crosstalk in VLSI Circuits.

[BibT_eX]

[DOI]

Haydar Hadi

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

2001

A low-power high-performance current-mode multiport SRAM.

[BibT_eX]

[DOI]

Muhammad M. Khellah

IEEE Trans. Very Large Scale Integr. Syst., 2001

Dynamic current mode logic (DyCML): a new low-power high-performance logic style.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2001

Split-Gate Logic circuits for multi-threshold technologies.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

Low-power design of decimation filters for a digital IF receiver.

[BibT_eX]

[DOI]

Brian A. White

IEEE Trans. Very Large Scale Integr. Syst., 2000

Fast and efficient parametric modeling of contact-to-substratecoupling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Low-power direct digital frequency synthesis for wireless communications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2000

High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

A contention-free domino logic for scaled-down CMOS technologies with ultra low threshold voltages.

[BibT_eX]

[DOI]

Mohab H. Anis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

An Efficient and Accurate Model for RF/Microwave Spiral Inductors Using Microstrip Lines Theory.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Low power high speed analog-to-digital converter for wireless communications.

[BibT_eX]

[DOI]

A. E. Hussein

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

A fully-integrated low phase-noise nested-loop PLL for frequency synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

Dynamic current mode logic (DyCML), a new low-power high-performance logic family.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

Effect of technology scaling on digital CMOS logic styles.

[BibT_eX]

[DOI]

Mohab H. Anis

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999

Differential PLL for wireless applications using differential CMOS LC-VCO and differential charge pump.

[BibT_eX]

[DOI]

Ayman ElSayed

Akbar Ali

Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

A formulation for quick evaluation and optimization of digital CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A low power monolithic subsampled phase-locked loop architecture for wireless transceivers.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A low-power CMOS frequency synthesizer design methodology for wireless applications.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A Low-Voltage High-Performance Differential Static Logic (LVDSL) family.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A Fast Parametric Model for Contact-Substrate Coupling.

[BibT_eX]

Proceedings of the VLSI: Systems on a Chip, 1999

Delay Optimization of CMOS Logic Circuits Using Closed-Form Expressions.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design, 1999

A Novel Low Power Low Phase-Noise PLL Architecture for Wireless Transceivers.

[BibT_eX]

[DOI]

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Fully integrated low phase-noise PLLs using closed-loop voltage-to-frequency converter architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

A low-power direct digital frequency synthesizer architecture for wireless communications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998

Transient Phenomena in High Speed Bipolar Devices.

[BibT_eX]

[DOI]

VLSI Design, 1998

Modeling and comparing CMOS implementations of the C-element.

[BibT_eX]

[DOI]

Jo C. Ebergen

IEEE Trans. Very Large Scale Integr. Syst., 1998

Low-Power Design of Finite Field Multipliers for Wireless Applications.

[BibT_eX]

[DOI]

Amr G. Wassal

M. Anwarul Hasan

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Effective Capacitance Macro-Modelling for Architectural-Level Power Estimation.

[BibT_eX]

[DOI]

Muhammad M. Khellah

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

A Low-Power High-Performance Embedded SRAM Macrocell.

[BibT_eX]

[DOI]

Muhammad M. Khellah

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997

VLSI compressor design with applications to digital neural networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1997

Low-power BiCMOS circuits for high-speed interchip communication.

[BibT_eX]

[DOI]

Duljit S. Malhi

IEEE J. Solid State Circuits, 1997

A programmable power-efficient decimation filter for software radios.

[BibT_eX]

[DOI]

Emad N. Farag

Ran-Hong Yan

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Optimizing CMOS Implementations of the C-element.

[BibT_eX]

[DOI]

Jo C. Ebergen

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996

A parallel digital layered perceptrons implementation.

[BibT_eX]

[DOI]

Neural Parallel Sci. Comput., 1996

Mapping neural networks onto systolic arrays.

[BibT_eX]

[DOI]

Neural Parallel Sci. Comput., 1996

Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1996

Power dissipation analysis and optimization of deep submicron CMOS digital circuits.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1996

All-N-logic high-speed true-single-phase dynamic CMOS logic.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1996

Circuit techniques for CMOS low-power high-performance multipliers.

[BibT_eX]

[DOI]

Issam S. Abu-Khater

Abdellatif Bellaouar

IEEE J. Solid State Circuits, 1996

A Digital Perceptron Learning Implementation with Look-up Table Feedback Layer.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 1996

A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element.

[BibT_eX]

[DOI]

Jo C. Ebergen

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Low-power subband coding algorithm.

[BibT_eX]

[DOI]

Emad N. Farag

Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

Low-Power Implementation of Discrete Cosine Transform.

[BibT_eX]

[DOI]

Emad N. Farag

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995

Active-pull-down nonthreshold logic BiCMOS circuits for high-speed low-power applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, June, 1995

Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 V supply voltage regime.

[BibT_eX]

[DOI]

Abdellatif Bellaouar

Sherif H. K. Embabi

IEEE J. Solid State Circuits, June, 1995

Low-power CMOS/BiCMOS drivers and receivers for on-chip interconnects.

[BibT_eX]

[DOI]

Abdellatif Bellaouar

Issam S. Abu-Khater

IEEE J. Solid State Circuits, June, 1995

Novel high speed circuit structures for BiCMOS environment.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, May, 1995

Differential BiCMOS logic circuits: fault characterization and design-for-testability.

[BibT_eX]

[DOI]

Shaahin Hessabi

Mohamed Y. Osman

IEEE Trans. Very Large Scale Integr. Syst., 1995

TRASIM: compact and efficient two-dimensional transient simulator for arbitrary planar semiconductor devices.

[BibT_eX]

[DOI]

Michael S. Obrecht

Edwin L. Heasell

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

A programmable neural network architecture using BiCMOS technology.

[BibT_eX]

[DOI]

Neural Parallel Sci. Comput., 1995

Power Dissipation in Deep Submicron CMOS Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Circuit/architecture for low-power high-performance 32-bit adder.

[BibT_eX]

[DOI]

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

1994

High-speed dynamic reference voltage (DRV) CMOS/ECL interface circuits.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, October, 1994

Highly testable design of BiCMOS logic circuits.

[BibT_eX]

[DOI]

Mohamed Y. Osman

IEEE J. Solid State Circuits, June, 1994

Full-swing Schottky BiCMOS/BiNMOS and the effects of operating frequency and supply voltage scaling.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, June, 1994

Schottky merged BiCMOS structures.

[BibT_eX]

[DOI]

Samir S. Rofail

IEEE J. Solid State Circuits, March, 1994

Novel low-voltage low-power full-swing BiCMOS circuits.

[BibT_eX]

[DOI]

Michael S. Obrecht

IEEE J. Solid State Circuits, February, 1994

An accurate analytical propagation delay model for high-speed CML bipolar circuits.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, January, 1994

Mixed analog/digital hardware synthesis of artificial neural networks.

[BibT_eX]

[DOI]

Arun Achyuthan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Pipelined architecture for neural-network-based speech recognition.

[BibT_eX]

[DOI]

Li Deng

Neural Parallel Sci. Comput., 1994

Analysis of the correlation structure for a neural predictive model with application to speech recognition.

[BibT_eX]

[DOI]

Li Deng

Khaled Hassanein

Neural Networks, 1994

Fuzzy Clustering Neural Network (FCNN): Competitive Learning and Parallel Architecture.

[BibT_eX]

[DOI]

Mohamed Kamel

J. Intell. Fuzzy Syst., 1994

BiCMOS Active-Pull-Down Non-Threshold Logic Cicuits for High-Speed Low-Power Applications.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

An All-N-Logic High-Speed Single-Phase Dynamic CMOS Logic.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Vowel classification using a neural predictive HMM: a discriminative training approach.

[BibT_eX]

[DOI]

Khaled Hassanein

Li Deng

Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994

Low-power differential CML and ECL BiCMOS circuit techniques.

[BibT_eX]

[DOI]

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

1993

Global optimization approach for architectural synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Modular switched-resistor ANN chip for character recognition using novel parallel VLSI architecture.

[BibT_eX]

Sameh Ebrahim Rehan

Neural Parallel Sci. Comput., 1993

Analog neural network building blocks based on current mode subthreshold operation.

[BibT_eX]

L. Song

Anthony Vannelli

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Minimum description length pruning and maximum mutual information training of adaptive probabilistic neural networks.

[BibT_eX]

[DOI]

Waleed Fakhr

Proceedings of International Conference on Neural Networks (ICNN'88), San Francisco, CA, USA, March 28, 1993

1992

The digi-neocognitron: a digital neocognitron neural network model for VLSI.

[BibT_eX]

[DOI]

Brian A. White

IEEE Trans. Neural Networks, 1992

STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits.

[BibT_eX]

[DOI]

J. Paul Harvey

Bosco Leung

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Testing and design for testability of BiCMOS logic circuits.

[BibT_eX]

[DOI]

Aly Ezzat Salama

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1991

Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 28th Design Automation Conference, 1991

1990

A fast learning technique for the multilayer perceptron.

[BibT_eX]

[DOI]

Waleed Fakhr

Proceedings of the IJCNN 1990, 1990

1989

Architectural synthesis for DSP silicon compilers.

[BibT_eX]

[DOI]

Baher Haroun

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

ACE: A Hierarchical Graphical Interface for Architectual Synthesis.

[BibT_eX]

[DOI]

O. A. Buset

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

Integrated design and test synthesis.

[BibT_eX]

[DOI]

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

Automatic synthesis of a multi-bus architecture for DSP.

[BibT_eX]

[DOI]

Baher Haroun

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

VLSI Design Synthesis with Testability.

[BibT_eX]

[DOI]

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

Symbolic Layout for Bipolar and MOS VLSI.

[BibT_eX]

[DOI]

Kevin S. B. Szabó

James M. Leask

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

The user interface and program structure of a graphical VLSI layout editor.

[BibT_eX]

[DOI]

Kevin S. B. Szabó

Proceedings of the SIGCHI/GI Conference on Human Factors in Computing Systems and Graphics Interface, 1987

1984

The icewater language and interpreter.

[BibT_eX]

[DOI]

Patrick A. D. Powell

Proceedings of the 21st Design Automation Conference, 1984

1982

WATPC: A Computer-Aided Design Package for Digital Bipolar Integrated Circuits.

[BibT_eX]

[DOI]

A. R. Teene

David J. Roulston

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1982

1976

Logic Design Using EFL Structures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1976

1975

Two-Level Emitter-Function Logic Structures for Logic-in-Memory Computers.

[BibT_eX]

[DOI]