Shawki Areibi

According to our database1, Shawki Areibi authored at least 80 papers between 1993 and 2020.

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Bibliography

2020
Machine Learning for Congestion Management and Routability Prediction within FPGA Placement.
ACM Trans. Design Autom. Electr. Syst., 2020

Multisource Domain Adaptation for Remote Sensing Using Deep Neural Networks.
IEEE Trans. Geosci. Remote. Sens., 2020

An Adaptive Analytic FPGA Placement Framework based on Deep-Learning.
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

A Deep-Learning Framework for Predicting Congestion During FPGA Placement.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019
Novel Congestion-estimation and Routability-prediction Methods based on Machine Learning for Modern FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2019

Enhancing the Performance of FPGA Congestion Management via Supervised Learning.
Proceedings of the 31st International Conference on Microelectronics, 2019

A Deep Learning Framework to Predict Routability for FPGA Circuit Placement.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

A Flat Timing-Driven Placement Flow for Modern FPGAs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
GPlace3.0: Routability-Driven Analytic Placer for UltraScale FPGA Architectures.
ACM Trans. Design Autom. Electr. Syst., 2018

Corrigendum to "Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm".
Int. J. Reconfigurable Comput., 2018

Corrigendum to "PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability".
Int. J. Reconfigurable Comput., 2018

Corrigendum to "An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization".
Int. J. Reconfigurable Comput., 2018

Stochastic Layer-Wise Precision in Deep Neural Networks.
Proceedings of the Thirty-Fourth Conference on Uncertainty in Artificial Intelligence, 2018

An Effective FPGA Placement Flow Selection Framework using Machine Learning.
Proceedings of the 30th International Conference on Microelectronics, 2018

Machine-Learning Based Congestion Estimation for Modern FPGAs.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
Domain Adaptation Using Representation Learning for the Classification of Remote Sensing Images.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2017

Automatic Flow Selection and Quality-of-Result Estimation for FPGA Placement.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Hardware accelerators for the K-nearest neighbor algorithm using high level synthesis.
Proceedings of the 29th International Conference on Microelectronics, 2017

A Machine Learning Framework for FPGA Placement (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016
An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems.
Int. J. Reconfigurable Comput., 2016

Deep Learning on FPGAs: Past, Present, and Future.
CoRR, 2016

An Efficient Framework for Floor-plan Prediction of Dynamic Runtime Reconfigurable Systems.
CoRR, 2016

Design exploration of ASIP architectures for the K-Nearest Neighbor machine-learning algorithm.
Proceedings of the 28th International Conference on Microelectronics, 2016

GPlace: a congestion-aware placement tool for ultrascale FPGAs.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Efficient algorithm selection for packet classification using machine learning.
Proceedings of the 21st IEEE International Workshop on Computer Aided Modelling and Design of Communication Links and Networks, 2016

Q-learning enhanced gradient based routing for balancing energy consumption in WSNs.
Proceedings of the 21st IEEE International Workshop on Computer Aided Modelling and Design of Communication Links and Networks, 2016

2015
Efficient Mapping and Allocation of Execution Units to Task Graphs using an Evolutionary Framework.
SIGARCH Comput. Archit. News, 2015

Scalable analytic placement for FPGA on GPGPU.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

2014
A Low-Power Scalable Stream Compute Accelerator for General Matrix Multiply (GEMM).
VLSI Design, 2014

Advancing genetic algorithm approaches to field programmable gate array placement with enhanced recombination operators.
Evol. Intell., 2014

Comparing Classifiers in Historical Census Linkage.
Proceedings of the 2014 IEEE International Conference on Data Mining Workshops, 2014

2013
Architecture Exploration Based on GA-PSO Optimization, ANN Modeling, and Static Scheduling.
VLSI Design, 2013

Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm.
Int. J. Reconfigurable Comput., 2013

An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization.
Int. J. Reconfigurable Comput., 2013

An efficient application-specific instruction-set processor for packet classification.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

An adaptive encryption based genetic algorithms for medical images.
Proceedings of the IEEE International Workshop on Machine Learning for Signal Processing, 2013

2012
An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C.
VLSI Design, 2012

A scalable pipelined architecture for real-time computation of MLP-BP neural networks.
Microprocess. Microsystems, 2012

Efficient On-line Hardware/Software Task Scheduling for Dynamic Run-time Reconfigurable Systems.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

A Sequential Ensemble Classification (SEC) System for Tackling the Problem of Unbalance Learning: A Case Study.
Proceedings of the 11th International Conference on Machine Learning and Applications, 2012

A Dynamic Sampling Framework for Multi-class Imbalanced Data.
Proceedings of the 11th International Conference on Machine Learning and Applications, 2012

2011
StarPlace: A new analytic method for FPGA placement.
Integr., 2011

PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability.
Int. J. Reconfigurable Comput., 2011

GBSA: A group based search algorithm for packet classification.
Proceedings of the 7th International Wireless Communications and Mobile Computing Conference, 2011

2010
Implementation Approaches Trade-Offs for WiMax OFDM Functions on Reconfigurable Platforms.
ACM Trans. Reconfigurable Technol. Syst., 2010

A Power-Efficient Multipin ILP-Based Routing Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Strength Pareto Particle Swarm Optimization and Hybrid EA-PSO for Multi-Objective Optimization.
Evol. Comput., 2010

An investigation of parallel memetic algorithms for VLSI circuit partitioning on multi-core computers.
Proceedings of the 23rd Canadian Conference on Electrical and Computer Engineering, 2010

2009
A Multilevel Congestion-Based Global Router.
VLSI Design, 2009

Meta-Heuristic Based Techniques for FPGA Placement: A Study.
Int. J. Comput. Their Appl., 2009

Near-linear wirelength estimation for FPGA placement.
Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

HW/SW co-design architecture exploration for VLSI maze routing.
Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009

2008
IEEE802.16-2004 OFDM functions implementation on FPGAS with design exploration.
Proceedings of the FPL 2008, 2008

2007
The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study.
IEEE Trans. Neural Networks, 2007

An ILP based hierarchical global routing approach for VLSI ASIC design.
Optim. Lett., 2007

A hardware Memetic accelerator for VLSI circuit partitioning.
Comput. Electr. Eng., 2007

Window Based Prototype Filter Design for Highly Oversampled Filter Banks in Audio Applications.
Proceedings of the IEEE International Conference on Acoustics, 2007

2006
An FPGA Implementation of the LMS Adaptive Filter for Audio Processing.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

2005
A Genetic Algorithm Hardware Accelerator for VLSI Circuit Partitioning.
Int. J. Comput. Their Appl., 2005

A Handel-C implementation of the back-propagation algorithm on field programmable gate arrays.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005

A Low-Power Partitioning Methodology by Maximizing Sleep Time and Minimizing Cut Nets.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

2004
Effective Memetic Algorithms for VLSI Design = Genetic Algorithms + Local Search + Multi-Level Clustering.
Evol. Comput., 2004

Fast techniques for standby leakage reduction in MTCMOS circuits.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

An Island-Based GA Implementation for VLSI Standard-Cell Placement.
Proceedings of the Genetic and Evolutionary Computation, 2004

A Fast Hierarchical Approach to FPGA Placement.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003
Design and optimization of multithreshold CMOS (MTCMOS) circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Tabu Search: Implementation & Complexity Analysis for Netlist Partitioning.
Int. J. Comput. Their Appl., 2003

2002
An Adaptive Genetic Algorithm For Multi Objective Flexible Manufacturing Systems.
Proceedings of the GECCO 2002: Proceedings of the Genetic and Evolutionary Computation Conference, 2002

Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique.
Proceedings of the 39th Design Automation Conference, 2002

Global Placement Techniques for VLSI Physical Design Automation.
Proceedings of the 15th International Conference on Computer Applications in Industry and Engineering, 2002

Feasibility of Floating-Point Arithmetic in FPGA based ANNs.
Proceedings of the 15th International Conference on Computer Applications in Industry and Engineering, 2002

Hardware Implementation of Genetic Algorithms for VLSI Design.
Proceedings of the 15th International Conference on Computer Applications in Industry and Engineering, 2002

Advanced P2P Architecture Using Autonomous Agents.
Proceedings of the 15th International Conference on Computer Applications in Industry and Engineering, 2002

2001
A new model for macrocell partitioning.
Proceedings of the ISCA 16th International Conference Computers and Their Applications, 2001

2000
Tabu Search: A Meta Heuristic for Netlist Partitioning.
VLSI Design, 2000

1999
Attractor-repeller approach for global placement.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1996
A GRASP clustering technique for circuit partitioning.
Proceedings of the Satisfiability Problem: Theory and Applications, 1996

1993
Circuit Partitioning Using a Tabu Search Approach.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Advanced Search Techniques for Circuit Partitioning.
Proceedings of the Quadratic Assignment and Related Problems, 1993


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