Mohamed Zahran

Affiliations:
  • New York University, Computer Science Department, NY, USA


According to our database1, Mohamed Zahran authored at least 27 papers between 2002 and 2019.

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Bibliography

2019
A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity.
J. Parallel Distributed Comput., 2019

Parallel Computing At The Undergraduate Level: Lessons Learned and Insights.
Proceedings of the Workshop on Computer Architecture Education, 2019

GPU-Accelerated Decoding of Integer Lists.
Proceedings of the 28th ACM International Conference on Information and Knowledge Management, 2019

2017
SACAT: Streaming-Aware Conflict-Avoiding Thrashing-Resistant GPGPU Cache Management Scheme.
IEEE Trans. Parallel Distributed Syst., 2017

Heterogeneous computing: here to stay.
Commun. ACM, 2017

Optimal Bandwidth Selection for Kernel Regression Using a Fast Grid Search and a GPU.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Space-Efficient Pointwise Computation of the Distance Transform on GPUs.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

2015
Efficient utilization of GPGPU cache hierarchy.
Proceedings of the 8th Workshop on General Purpose Processing using GPUs, 2015

2013
Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach.
IEEE Des. Test, 2013

2012
Architecture Support for Dynamic Integrity Checking.
IEEE Trans. Inf. Forensics Secur., 2012

2011
Improving GPU Robustness by making use of faulty parts.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Are hardware performance counters a cost effective way for integrity checking of programs.
Proceedings of the sixth ACM workshop on Scalable trusted computing, 2011

2010
On the Power Management of Simultaneous Multithreading Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2010

On-chip sensor-driven efficient thermal profile estimation algorithms.
ACM Trans. Design Autom. Electr. Syst., 2010

Feasibility study of dynamic Trusted Platform Module.
Proceedings of the 28th International Conference on Computer Design, 2010

Global management of cache hierarchies.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
Challenges and opportunities at all levels: interactions among operating systems, compilers, and multicore processors.
ACM SIGOPS Oper. Syst. Rev., 2009

2008
Chip level thermal profile estimation using on-chip temperature sensors.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
Non-Inclusion Property in Multi-Level Caches Revisited.
Int. J. Comput. Their Appl., 2007

2006
RHT: A Context-Based Return Address Predictor.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

Bandwidth-Friendly Cache Hierarchy.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

2005
Hybrid compiler and microarchitecture technique for cache traffic optimization.
Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures, 2005

2004
Productivity Analysis of the UPC Language.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003
On cache memory hierarchy for Chip-Multiprocessor.
SIGARCH Comput. Archit. News, 2003

Dynamic Thread Resizing for Speculative Multithreaded Processors.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002
A Feasibility Study of Hierarchical Multithreading.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Return-Address Prediction in Speculative Multithreaded Environments.
Proceedings of the High Performance Computing, 2002


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