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Ajay Taparia

According to our database1, Ajay Taparia authored at least 4 papers between 2008 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
A 12 bit, 2-MS/s, 0.016-mm<sup>2</sup> column-parallel readout cyclic ADC, having 50% reduced slew rate requirement due to feed-forward spike eliminator.
[BibTeX]
[DOI]
Saikrishna Ganta
,
Alfredo Tomasini
,
Ajay Taparia
,
Taehee Cho
,
Mandar Kulkarni
,
Ozan Erdogan
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2011
CS-CMOS: A Low-Noise Logic Family for Mixed Signal SoCs.
[BibTeX]
[DOI]
Ajay Taparia
,
Bhaskar Banerjee
,
Thayamkulangara R. Viswanathan
IEEE Trans. Very Large Scale Integr. Syst., 2011

Power-Supply Noise Reduction Using Active Inductors in Mixed-Signal Systems.
[BibTeX]
[DOI]
Ajay Taparia
,
Bhaskar Banerjee
,
Thayamkulangara R. Viswanathan
IEEE Trans. Very Large Scale Integr. Syst., 2011

2008
Low-power short-channel single-ended current-steered CMOS logic-gate for mixed-signal systems.
[BibTeX]
[DOI]
Ajay Taparia
,
Thayamkulangara R. Viswanathan
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008


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