Ajith Pasqual

According to our database, Ajith Pasqual authored at least 20 papers between 1998 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

A Four-Step Method to Synthesize a DC-DC Converter for Multi-Inductor Realizable Arbitrary Voltage Conversion Ratio.

Thilina S. Ambagahawaththa, Dulika Nayanasiri, Ajith Pasqual

IEEE Trans. Ind. Electron., 2022

2021

Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks.

Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual

CoRR, 2021

2019

FPGA IP for Real-time 4K HDR Image Decoding in VR Devices.

Kamlakannan Kamalavasan, Ratnasegar Natheesan, Kathirgamaraja Pradeep, Sivakumaran Gowthaman, Sivakaneshan Aravinth, Ajith Pasqual

Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

Scalable High Performance SDN Switch Architecture on FPGA for Core Networks.

Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

SMPTE ST 2110 Compliant Scalable Architecture on FPGA for end to end Uncompressed Professional Video Transport Over IP Networks.

Nisal Ranasinghe, Ravindu Bangamuarachchi, Jayath Seneviratne, Achini Jayawardane, Ajith Pasqual, R. M. A. U. Senarath

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018

EdgeNet: SqueezeNet like Convolution Neural Network on Embedded FPGA.

Kathirgamaraja Pradeep, Kamalakkannan Kamalavasan, Ratnasegar Natheesan, Ajith Pasqual

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A Novel Low-Complexity VLSI Architecture for an EEG Feature Extraction Platform.

Dakila Serasinghe, Duvindu Piyasena, Ajith Pasqual

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutiosnal Neural Networks.

Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual

Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017

FPAA and FPGA based universal sensor node design.

Ayanga D. Kalupahana, Nisal Hemadasa, Nipun Wijerathne, Anuranga Ranasinghe, Ajith Pasqual

Proceedings of the Eleventh International Conference on Sensing Technology, 2017

Hybrid Software Defined Networking Controller.

Kosala Perera, Udesh Gunarathne, Binal Chathuranga, Chamika Ramanayake, Ajith Pasqual

Proceedings of the 14th International Joint Conference on e-Business and Telecommunications (ICETE 2017), 2017

Runtime rule-reconfigurable high throughput NIPS on FPGA.

P. M. K. Tharaka, D. M. D. Wijerathne, Navoda Perera, Dinushan Vishwajith, Ajith Pasqual

Proceedings of the International Conference on Field Programmable Technology, 2017

High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension.

Rishan Senanayake, Namitha Liyanage, Sasindu Wijeratne, Sachille Atapattu, Kasun Athukorala, P. M. K. Tharaka, Geethan Karunaratne, R. M. A. U. Senarath, Ishantha Perera, Ashen Ekanayake, Ajith Pasqual

Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016

4K Real-Time HEVC Decoder on an FPGA.

Maleen Abeydeera, Manupa Karunaratne, Geethan Karunaratne, Kalana De Silva, Ajith Pasqual

IEEE Trans. Circuits Syst. Video Technol., 2016

High performance flow matching architecture for OpenFlow data plane.

Viduranga Bandara Wijekoon, T. M. Dananjaya, P. H. Kariyawasam, S. Iddamalgoda, Ajith Pasqual

Proceedings of the 2016 IEEE Conference on Network Function Virtualization and Software Defined Networks (NFV-SDN), 2016

Real time all intra HEVC HD encoder on FPGA.

Sachille Atapattu, Namitha Liyanage, Nisal Menuka, Ishantha Perera, Ajith Pasqual

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015

HEVC inverse transform architecture utilizing coefficient sparsity.

Maleen Abeydeera, Ajith Pasqual

Proceedings of the 2015 IEEE International Conference on Image Processing, 2015

2012

High performance parallel packet Classification architecture with Popular Rule Caching.

Samoda Gamage, Ajith Pasqual

Proceedings of the 18th IEEE International Conference on Networks, 2012

2008

Impact of ICT on learning and teaching.

Ravina Panangalage, Ajith Pasqual

Proceedings of the Citizens, 2008

1999

Software Based Object Tracking with Visual Feature Integration.

Ajith Pasqual, Hidenori Takeshima, Kiyoharu Aizawa

Proceedings of the 1999 International Conference on Image Processing, 1999

1998

Selection/Substitution of Visual Features for Object Tracking.

Ajith Pasqual, Kiyoharu Aizawa, Mitsutoshi Hatori

Proceedings of IAPR Workshop on Machine Vision Applications, 1998