Geethan Karunaratne

Orcid: 0000-0002-0805-4789

According to our database1, Geethan Karunaratne authored at least 37 papers between 2016 and 2024.

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Bibliography

2024
Limits of Transformer Language Models on Learning Algorithmic Compositions.
CoRR, 2024

Zero-shot Classification using Hyperdimensional Computing.
CoRR, 2024

2023
Generalized Key-Value Memory to Flexibly Adjust Redundancy in Memory-Augmented Networks.
IEEE Trans. Neural Networks Learn. Syst., December, 2023

Graphene-Based Wireless Agile Interconnects for Massive Heterogeneous Multi-Chip Processors.
IEEE Wirel. Commun., August, 2023

WHYPE: A Scale-Out Architecture With Wireless Over-the-Air Majority for Scalable In-Memory Hyperdimensional Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

Raw data related to In-memory factorization of holographic perceptual representations.
Dataset, February, 2023

Few-Shot Continual Learning Based on Vector Symbolic Architectures.
Proceedings of the Compendium of Neurosymbolic Artificial Intelligence, 2023

In-memory Vector Symbolic Architectures.
PhD thesis, 2023

TCNCA: Temporal Convolution Network with Chunked Attention for Scalable Sequence Processing.
CoRR, 2023

Factorizers for Distributed Sparse Block Codes.
CoRR, 2023

MIMONets: Multiple-Input-Multiple-Output Neural Networks Exploiting Computation in Superposition.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Decoding Superpositions of Bound Symbols Represented by Distributed Representations.
Proceedings of the 17th International Workshop on Neural-Symbolic Learning and Reasoning, 2023

2022
HERMES-Core - A 1.59-TOPS/mm<sup>2</sup> PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs.
IEEE J. Solid State Circuits, 2022

A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference.
CoRR, 2022

In-memory factorization of holographic perceptual representations.
CoRR, 2022

Wireless On-Chip Communications for Scalable In-memory Hyperdimensional Computing.
Proceedings of the International Joint Conference on Neural Networks, 2022

In-memory Realization of In-situ Few-shot Continual Learning with a Dynamically Evolving Explicit Memory.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

Constrained Few-shot Class-incremental Learning.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Energy Efficient In-Memory Hyperdimensional Encoding for Spatio-Temporal Signal Processing.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

ChewBaccaNN: A Flexible 223 TOPS/W BNN Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH).
Proceedings of the CF '21: Computing Frontiers Conference, 2021

End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet?
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

Real-time Language Recognition using Hyperdimensional Computing on Phase-change Memory Array.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors.
CoRR, 2020

Robust High-dimensional Memory-augmented Neural Networks.
CoRR, 2020

Mixed-precision deep learning based on computational memory.
CoRR, 2020

ESSOP: Efficient and Scalable Stochastic Outer Product Architecture for Deep Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Deep learning acceleration based on in-memory computing.
IBM J. Res. Dev., 2019

In-memory hyperdimensional computing.
CoRR, 2019

Computational memory-based inference and training of deep neural networks.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Applications of Computation-In-Memory Architectures based on Memristive Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
XNORBIN: A 95 TOp/s/W hardware accelerator for binary convolutional neural networks.
Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

2017
High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016
4K Real-Time HEVC Decoder on an FPGA.
IEEE Trans. Circuits Syst. Video Technol., 2016


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