Akira Yamawaki
Orcid: 0000-0002-7821-3597Affiliations:
- Kyushu Institute of Technology, Japan
According to our database1,
Akira Yamawaki
authored at least 35 papers
between 2001 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Light-weight color image conversion like pencil drawing for high-level synthesized hardware.
Artif. Life Robotics, February, 2024
2023
An investigation of software describing methods to design dual background scrolling hardware in high-level synthesis.
Artif. Life Robotics, August, 2023
2022
Development of a general purpose verification environment for high-level-synthesis image processing hardware with support for dynamic partial reconfiguration.
Artif. Life Robotics, 2022
Development of a real camera system with high-level synthesised hardware of median-based dynamic background subtraction.
Artif. Life Robotics, 2022
Artif. Life Robotics, 2022
Memory Access Optimization for Former Process of Pencil Drawing Style Image Conversion in High-Level Synthesis.
Proceedings of the Parallel and Distributed Computing, Applications and Technologies, 2022
2021
Development of High Performance Hardware by High-Level Synthesis of Median-Based Dynamic Background Subtraction Method with Multiple Line Buffers.
Proceedings of the IEEE Region 10 Conference, 2021
Omnidirectional Background Scrolling in High-Level Synthesis Oriented Game Programing Library.
Proceedings of the IEEE Region 10 Conference, 2021
2020
Duplicating same argument of function to realize efficient hardware for high-level synthesis.
Artif. Life Robotics, 2020
A performance evaluation of read/write burst transfer by high-level synthesizable software for the alpha blending processing.
Artif. Life Robotics, 2020
2019
Artif. Life Robotics, 2019
Effect of Parallel Processing by Duplicating Histogram in Automatic Image Binarization for High-Level Synthesis.
Proceedings of the 20th International Conference on Parallel and Distributed Computing, 2019
Development of Filled Circle Drawing in High-Level Synthesis Oriented Game Programming Library.
Proceedings of the 20th International Conference on Parallel and Distributed Computing, 2019
2018
A Describing Method of an Image Processing Software in C for a High-Level Synthesis Considering a Function Chaining.
IEICE Trans. Inf. Syst., 2018
Describing Methods for High-level Synthesis of Histogram Generation and Their Evaluation.
Proceedings of the TENCON 2018, 2018
Proceedings of the TENCON 2018, 2018
2016
Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016
2015
Proceedings of the Software Engineering, 2015
Artif. Life Robotics, 2015
2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
A lightweight sensing method of tooth-touch sound for disabled person using remote controller.
Artif. Life Robotics, 2012
Proceedings of the IEEE/SICE International Symposium on System Integration, 2012
2010
A method using the same light sensor for detecting multiple events near a window in crimes involving intrusion into a home.
Artif. Life Robotics, 2010
Proceedings of the Computational Science and Its Applications, 2010
An Architecture of Prototyping System for Dynamic Partial Reconfiguration on FPGA.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010
2009
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009
An Efficient Comparative Evaluation to Buffering Methods for Window-based Image Processing Using Semi-programmable Hardware.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip.
Proceedings of the 13th International Conference on Parallel and Distributed Systems, 2007
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007
2005
Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor.
Proceedings of the 8th International Symposium on Parallel Architectures, 2005
An efficient parallel processing using a cache memory with synchronization on a Soc-multiprocessor.
Proceedings of the Third IASTED International Conference on Circuits, 2005
2004
Evaluation of mechanisms introduced to improve performance of TSVM cache.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2004
2002
Proceedings of the 9th International Conference on Parallel and Distributed Systems, 2002
2001
Syst. Comput. Jpn., 2001