Akshay Muraleedharan

According to our database, Akshay Muraleedharan authored at least 2 papers between 2019 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA.

T. Gokulan, Akshay Muraleedharan, Kuruvilla Varghese

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019

A 75-µW 2.4 GHz Wake-up Receiver in 65-nm CMOS for Neonatal Healthcare Application.

Kundan Kumar, Raghunath K. P, Akshay Muraleedharan, Javed S. Gaggatur, Gaurab Banerjee

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019