Kuruvilla Varghese

According to our database1, Kuruvilla Varghese authored at least 17 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


A RISC-V ISA Compatible Processor IP.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network.
IEEE Trans. Neural Networks Learn. Syst., 2018

FPGA Based Reconfigurable Coprocessor for Deep Convolutional Neural Network Training.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

A Custom Designed RISC-V ISA Compatible Processor for SoC.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

A high-throughput clock-less architecture for soft-output Viterbi detection.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Transparent FPGA based device for SQL DDoS mitigation.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

HD Resolution Intra Prediction Architecture for H.264 Decoder.
Proceedings of the 25th International Conference on VLSI Design, 2012

A scalable network port scan detection system on FPGA.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

In-channel Flow Control Scheme for Network-on-Chip.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Space Efficient Diagonal Linear Space Sequence Alignment.
Proceedings of the 10th IEEE International Conference on Bioinformatics and Bioengineering, 2010

Area optimized H.264 Intra prediction architecture for 1080p HD resolution.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

Power optimal Network-on-Chip interconnect design.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

A Scalable High Throughput Firewall in FPGA.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

Dynamically reconfigurable regular expression matching architecture.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008