Kuruvilla Varghese

According to our database, Kuruvilla Varghese authored at least 23 papers between 2008 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Design of a Multi-Core Compatible Linux Bootable 64-bit Out-of-Order RISC-V Processor Core.

Sajin S, Shubham Sunil Garag, Anuj Phegade, Deepshikha Gusain, Kuruvilla Varghese

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

Deep-Feature-Based Visual Odometry for Autonomous Emergency Parking.

Shrutheesh Raman Iyer, Kuruvilla Varghese, Raghu Krishnapuram, Panini Bhamidipati

Proceedings of the 2023 6th International Conference on Advances in Robotics, 2023

2022

Hardware Accelerator for Capsule Network based Reinforcement Learning.

Dola Ram, Suraj Panwar, Kuruvilla Varghese

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

A Soft RISC-V Vector Processor for Edge-AI.

V. Naveen Chander, Kuruvilla Varghese

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

High-Level Synthesis of Geant4 Particle Transport Application for FPGA.

Ramakant Joshi, Kuruvilla Varghese

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021

Network Emulation For Tele-driving Application Development.

Srikrishna Acharya, S. Sadgun S. Devanahalli, Alok Rawat, Kuruvilla Varghese, Pratik Sharma, Bharadwaj Amrutur, Ashish Joglekar, Raghu Krishnapuram, Yogesh Simmhan, Himanshu Tyagi

Proceedings of the 13th International Conference on COMmunication Systems & NETworkS, 2021

2020

A RISC-V ISA Compatible Processor IP.

Akshay Birari, Piyush Birla, Kuruvilla Varghese, Bharadwaj S. Amrutur

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA.

T. Gokulan, Akshay Muraleedharan, Kuruvilla Varghese

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2018

Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network.

Nimish Shah, Paragkumar Chaudhari, Kuruvilla Varghese

IEEE Trans. Neural Networks Learn. Syst., 2018

FPGA Based Reconfigurable Coprocessor for Deep Convolutional Neural Network Training.

Sajna Remi Clere, Sachin Sethumadhavan, Kuruvilla Varghese

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017

A Custom Designed RISC-V ISA Compatible Processor for SoC.

Kavya Sharat, Sumeet Bandishte, Kuruvilla Varghese, Bharadwaj S. Amrutur

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

A high-throughput clock-less architecture for soft-output Viterbi detection.

Arnab Dey, Sebin Jose, Kuruvilla Varghese, Shayan Garani Srinivasa

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016

A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA.

Saugata Datta, Kuruvilla Varghese, Shayan Garani Srinivasa

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015

Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA.

Sriram Venkateshan, Alap Patel, Kuruvilla Varghese

IEEE Trans. Very Large Scale Integr. Syst., 2015

2013

Transparent FPGA based device for SQL DDoS mitigation.

Karthikeyan Pandiyarajan, Srijith Haridas, Kuruvilla Varghese

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2012

HD Resolution Intra Prediction Architecture for H.264 Decoder.

Jimit Shah, K. S. Raghunandan, Kuruvilla Varghese

Proceedings of the 25th International Conference on VLSI Design, 2012

2011

A scalable network port scan detection system on FPGA.

Tejasvi Anand, Yagnesh Waghela, Kuruvilla Varghese

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

2010

In-channel Flow Control Scheme for Network-on-Chip.

Vrishali Vijay Nimbalkar, Kuruvilla Varghese

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Space Efficient Diagonal Linear Space Sequence Alignment.

Gandhi Arpit, Raghavendra Adiga, Kuruvilla Varghese

Proceedings of the 10th IEEE International Conference on Bioinformatics and Bioengineering, 2010

Area optimized H.264 Intra prediction architecture for 1080p HD resolution.

Jimit Shah, K. S. Raghunandan, Kuruvilla Varghese

Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

2009

Power optimal Network-on-Chip interconnect design.

G. Vikas, Joy Kuri, Kuruvilla Varghese

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008

A Scalable High Throughput Firewall in FPGA.

Gajanan S. Jedhe, Arun Ramamoorthy, Kuruvilla Varghese

Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

Dynamically reconfigurable regular expression matching architecture.

J. Divyasree, H. Rajashekar, Kuruvilla Varghese

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008