Alejandro Medina-Santiago

Orcid: 0000-0003-4468-9850

According to our database1, Alejandro Medina-Santiago authored at least 18 papers between 2012 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
A Hybrid Heuristic Algorithm for the Traveling Salesman Problem with Structured Initialization in Global-Local Search.
Algorithms, 2026

2025
Kinematic Fuzzy Logic-Based Controller for Trajectory Tracking of Wheeled Mobile Robots in Virtual Environments.
Symmetry, 2025

Road Event Detection and Classification Algorithm Using Vibration and Acceleration Data.
Algorithms, 2025

Ego-Motion Estimation for Autonomous Vehicles Based on Genetic Algorithms and CUDA Parallel Processing.
Algorithms, 2025

Fuzzy Linear Programming Formulation for Time Prediction in Product Delivery.
IEEE Access, 2025

2024
Multilayer Fuzzy Inference System for Predicting the Risk of Dropping Out of School at the High School Level.
IEEE Access, 2024

Fault Diagnosis for Takagi-Sugeno Model Wind Turbine Pitch System.
IEEE Access, 2024

2023
Diagnosis and Study of Mechanical Vibrations in Cargo Vehicles Using ISO 2631-1:1997.
Sensors, December, 2023

2022
Hypertension Diagnosis with Backpropagation Neural Networks for Sustainability in Public Health.
Sensors, 2022

A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors.
Sensors, 2022

2021
CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions.
Sensors, 2021

Intelligent Search of Values for a Controller Using the Artificial Bee Colony Algorithm to Control the Velocity of Displacement of a Robot.
Algorithms, 2021

2020
Digital System Design Using Standard NeuMOS Cells Applied in ADAS.
Circuits Syst. Signal Process., 2020

Adaptive Model IoT for Monitoring in Data Centers.
IEEE Access, 2020

2019
Reconfigurable arithmetic logic unit designed with threshold logic gates.
IET Circuits Devices Syst., 2019

2018
Lightweight Security Hardware Architecture Using DWT and AES Algorithms.
IEICE Trans. Inf. Syst., 2018

2014
An adaptive geometrically-complemented approach for ECG signal denoising.
Proceedings of the 11th International Conference on Electrical Engineering, 2014

2012
4-Bit Arithmetic Logic Unit (ALU) based on Neuron MOS Transistors.
Proceedings of the 9th International Conference on Electrical Engineering, 2012


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