Claudia Feregrino Uribe
Orcid: 0000-0001-9665-2203Affiliations:
- National Institute of Astrophysics, Optics and Electronics, Puebla, Mexico
According to our database1,
Claudia Feregrino Uribe
authored at least 112 papers
between 1999 and 2024.
Collaborative distances:
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Bibliography
2024
A novel partition strategy for efficient implementation of 3D Cellular Genetic Algorithms.
Microprocess. Microsystems, 2024
2023
On a self-recovery digital watermarking scheme robust against spatial and temporal attacks on compressed video.
J. Frankl. Inst., November, 2023
Expert Syst. Appl., November, 2023
Revocation in attribute-based encryption for fog-enabled internet of things: A systematic survey.
Internet Things, October, 2023
Artificial intelligence for IoMT security: A review of intrusion detection systems, attacks, datasets and Cloud-Fog-Edge architectures.
Internet Things, October, 2023
IoT Architecture and Security Mecanisms for an Energy Management System in a Smart Microgrid.
Proceedings of the 20th International Conference on Electrical Engineering, 2023
2022
Robust image hashing for content identification through contrastive self-supervised learning.
Neural Networks, 2022
Inf. Sci., 2022
ACM Comput. Surv., 2022
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2022
Proceedings of the 11th Mediterranean Conference on Embedded Computing, 2022
Proceedings of the IEEE Mexican International Conference on Computer Science, 2022
2021
Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES.
Sensors, 2021
A Compact FPGA-Based Accelerator for Curve-Based Cryptography in Wireless Sensor Networks.
J. Sensors, 2021
Expert Syst. Appl., 2021
Eng. Appl. Artif. Intell., 2021
Security on in-vehicle communication protocols: Issues, challenges, and future research directions.
Comput. Commun., 2021
2020
Expert Syst. Appl., 2020
A Double Fragmentation Approach for Improving Virtual Primary Key-Based Watermark Synchronization.
IEEE Access, 2020
2019
Pattern Recognit. Lett., 2019
Multim. Tools Appl., 2019
J. Parallel Distributed Comput., 2019
J. Parallel Distributed Comput., 2019
Temporal Copy-Move Forgery Detection and Localization Using Block Correlation Matrix.
J. Intell. Fuzzy Syst., 2019
Framework for audio reversible watermarking robust against content replacement with signal restoration capabilities.
J. Frankl. Inst., 2019
HQR-Scheme: A High Quality and resilient virtual primary key generation approach for watermarking relational data.
Expert Syst. Appl., 2019
IEEE Access, 2019
Proceedings of the IEEE Pacific Rim Conference on Communications, 2019
Proceedings of the Research and Practical Issues of Enterprise Information Systems, 2019
2018
On the design of hardware-software architectures for frequent itemsets mining on data streams.
J. Intell. Inf. Syst., 2018
IEICE Trans. Inf. Syst., 2018
2017
Multim. Tools Appl., 2017
Multim. Tools Appl., 2017
A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Approximate frequent itemsets mining on data streams using hashing and lexicographie order in hardware.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Audio Reversible Watermarking Scheme in the intDCT Domain with Modified Prediction Error Expansion.
Proceedings of the 5th ACM Workshop on Information Hiding and Multimedia Security, 2017
Proceedings of the 5th ACM Workshop on Information Hiding and Multimedia Security, 2017
2016
Intell. Data Anal., 2016
Proceedings of the 18th IEEE International Workshop on Multimedia Signal Processing, 2016
An FPGA Architecture to Accelerate the Burrows Wheeler Transform by Using a Linear Sorter.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016
2015
Microprocess. Microsystems, 2015
Expert Syst. Appl., 2015
An analysis of computational models for accelerating the subtractive pixel adjacency model computation.
Comput. Electr. Eng., 2015
Proceedings of the New Frontiers in Mining Complex Patterns - 4th International Workshop, 2015
Proceedings of the Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications, 2015
Proceedings of the Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications, 2015
2014
Res. Comput. Sci., 2014
Microprocess. Microsystems, 2014
IEICE Electron. Express, 2014
Comput. Electr. Eng., 2014
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Proceedings of the 9th International Conference for Internet Technology and Secured Transactions, 2014
Proceedings of the Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications, 2014
2013
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256.
Microprocess. Microsystems, 2013
Expert Syst. Appl., 2013
Area/performance trade-off analysis of an FPGA digit-serial <i>GF</i>(2<sup><i>m</i></sup>)GF(2m) Montgomery multiplier based on LFSR.
Comput. Electr. Eng., 2013
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
Proceedings of the Image and Video Technology - 6th Pacific-Rim Symposium, 2013
2012
Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10).
Int. J. Reconfigurable Comput., 2012
IEICE Electron. Express, 2012
Expert Syst. Appl., 2012
Digit. Signal Process., 2012
Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
2011
J. Signal Process. Syst., 2011
Bit-serial and digit-serial GF(2<sup>m</sup>)Montgomery multipliers using linear feedback shift registers.
IET Comput. Digit. Tech., 2011
Invited paper: Implementing digital data hiding algorithms in reconfigurable hardware - Experiences on teaching and research.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
2010
A Single Formula and its Implementation in FPGA for Elliptic Curve Point Addition Using Affine Representation.
J. Circuits Syst. Comput., 2010
IEICE Electron. Express, 2010
A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter.
Digit. Signal Process., 2010
Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11i standard.
Comput. Electr. Eng., 2010
Proceedings of the Advances in Pattern Recognition, 2010
On the Design of a Hardware-Software Architecture for Acceleration of SVM's Training Phase.
Proceedings of the Advances in Pattern Recognition, 2010
Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems.
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010
2009
IEICE Electron. Express, 2009
An area/performance trade-off analysis of a GF(2<sup>m</sup>) multiplier architecture for elliptic curve cryptography.
Comput. Electr. Eng., 2009
Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Proceedings of the 2009 Mexican International Conference on Computer Science, 2009
Proceedings of the 2009 Mexican International Conference on Computer Science, 2009
2008
IEICE Trans. Inf. Syst., 2008
Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description.
IEICE Trans. Inf. Syst., 2008
On the design and implementation of a RISC processor extension for the KASUMI encryption algorithm.
Comput. Electr. Eng., 2008
A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware Implementation.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter.
Proceedings of the FPL 2008, 2008
Proceedings of the 18th International Conference on Electronics, 2008
Proceedings of the 18th International Conference on Electronics, 2008
2007
Proceedings of the Intelligent Data Engineering and Automated Learning, 2007
Proceedings of the 17th International Conference on Electronics, 2007
Proceedings of the 17th International Conference on Electronics, 2007
Proceedings of the 17th International Conference on Electronics, 2007
2006
Parallel Hardware/Software Architecture for the BWT and LZ77 Lossless Data Compression Algorithms.
Computación y Sistemas, 2006
A Fast Elliptic Curve Based Key Agreement Protocol-on-Chip (PoC) for Securing Networked Embedded Systems.
Proceedings of the 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 2006
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006
Design and Implementation of an FPGA-Based 1.452-Gbps Non-pipelined AES Architecture.
Proceedings of the Computational Science and Its Applications, 2006
On the Design and Implementation of a High Performance Configurable Architecture for Testor Identification.
Proceedings of the Progress in Pattern Recognition, 2006
2005
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005
Proceedings of the 15th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2005), 28 February 2005, 2005
A Hardware Architecture for Elliptic Curve Cryptography and Lossless Data Compression.
Proceedings of the 15th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2005), 28 February 2005, 2005
2004
Proceedings of the 5th Mexican International Conference on Computer Science (ENC 2004), 2004
2003
Three video applications using an FPGA based pyramid implementation: Tracking, Mosaics and Stabilization.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003
Proceedings of the 4th Mexican International Conference on Computer Science (ENC 2003), 2003
2001
A novel approach for the hardware implementation of a PPMC statistical data compressor.
PhD thesis, 2001
Proceedings of the Field-Programmable Logic and Applications, 2001
Proceedings of the Field-Programmable Logic and Applications, 2001
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001
1999
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999