Alessandro Bardine

According to our database1, Alessandro Bardine authored at least 12 papers between 2006 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2014
Evaluation of Leakage Reduction Alternatives for Deep Submicron Dynamic Nonuniform Cache Architecture Caches.
IEEE Trans. VLSI Syst., 2014

2012
A real-time configurable NURBS interpolator with bounded acceleration, jerk and chord error.
Comput. Aided Des., 2012

2011
NUMA Caches.
Proceedings of the Encyclopedia of Parallel Computing, 2011

Energy Behaviour of NUCA Caches in CMPs.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Way adaptable D-NUCA caches.
IJHPSA, 2010

NURBS interpolator with confined chord error and tangential and centripetal acceleration control.
Proceedings of the International Conference on Ultra Modern Telecommunications, 2010

2009
Impact of on-chip network parameters on nuca cache performances.
IET Computers & Digital Techniques, 2009

A power-efficient migration mechanism for D-NUCA caches.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Performance Sensitivity of NUCA Caches to On-Chip Network Parameters.
Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

Leveraging Data Promotion for Low Power D-NUCA Caches.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Improving power efficiency of D-NUCA caches.
SIGARCH Computer Architecture News, 2007

2006
Analysis of embedded video coder systems: a system-level approach.
SIGARCH Computer Architecture News, 2006


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