Cosimo Antonio Prete

IEEE Access, 2024

2023

U-Nets and Multispectral Images for Detecting the Surface Water of Rivers via SAR Images.

[BibT_eX]

[DOI]

Diana Orlandi

Federico A. Galatolo

Alessandro La Rosa

Carolina Pagli

Proceedings of the Geographical Information Systems Theory, Applications and Management, 2023

2022

in-Car Entertainment via Group-wise Temporary Mobile Social Networking.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Vehicle Technology and Intelligent Transport Systems, 2022

Using Emotion Recognition and Temporary Mobile Social Network in On-Board Services for Car Passengers.

[BibT_eX]

[DOI]

Antonio Di Tecco

Proceedings of the Smart Cities, Green Technologies, and Intelligent Transport Systems, 2022

2021

Fast Blob and Air Line Defects Detection for High Speed Glass Tube Production Lines.

[BibT_eX]

[DOI]

Antonio Di Tecco

J. Imaging, 2021

A pre-processing technique to decrease inspection time in glass tube production lines.

[BibT_eX]

[DOI]

IET Image Process., 2021

2020

Row-level algorithm to improve real-time performance of glass tube defect detection in the production phase.

[BibT_eX]

[DOI]

IET Image Process., 2020

2019

Algorithms for the Detection of Blob Defects in High Speed Glass Tube Production Lines.

[BibT_eX]

[DOI]

Proceedings of the IEEE 8th International Workshop on Advances in Sensors and Interfaces, 2019

2018

Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2018

Stock Price Forecasting Over Adaptive Timescale Using Supervised Learning and Receptive Fields.

[BibT_eX]

[DOI]

Proceedings of the Mining Intelligence and Knowledge Exploration, 2018

2015

An architecture to integrate IEC 61131-3 systems in an IEC 61499 distributed solution.

[BibT_eX]

[DOI]

Stefano Campanelli

Comput. Ind., 2015

2014

Evaluation of Leakage Reduction Alternatives for Deep Submicron Dynamic Nonuniform Cache Architecture Caches.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Social and Q&A interfaces for app download.

[BibT_eX]

[DOI]

Inf. Process. Manag., 2014

2013

A Social-Feedback Enriched Interface for Software Download.

[BibT_eX]

[DOI]

J. Organ. End User Comput., 2013

2012

A real-time configurable NURBS interpolator with bounded acceleration, jerk and chord error.

[BibT_eX]

[DOI]

Comput. Aided Des., 2012

Integration of existing IEC 61131-3 systems in an IEC 61499 distributed solution.

[BibT_eX]

[DOI]

Stefano Campanelli

Proceedings of 2012 IEEE 17th International Conference on Emerging Technologies & Factory Automation, 2012

2011

NUMA Caches.

[BibT_eX]

[DOI]

Proceedings of the Encyclopedia of Parallel Computing, 2011

Eighth MEDEA Workshop.

[BibT_eX]

[DOI]

Trans. High Perform. Embed. Archit. Compil., 2011

2010

Way adaptable D-NUCA caches.

[BibT_eX]

[DOI]

Int. J. High Perform. Syst. Archit., 2010

Feedback-Driven Restructuring of Multi-threaded Applications for NUCA Cache Performance in CMPs.

[BibT_eX]

[DOI]

Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010

NURBS interpolator with confined chord error and tangential and centripetal acceleration control.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Ultra Modern Telecommunications, 2010

Re-NUCA: Boosting CMP Performance Through Block Replication.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Impact of on-chip network parameters on nuca cache performances.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2009

Analysis of Performance Dependencies in NUCA-Based CMP Systems.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing, 2009

An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

A power-efficient migration mechanism for D-NUCA caches.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Performance Sensitivity of NUCA Caches to On-Chip Network Parameters.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

Special track on Embedded Systems: Applications, Solutions, and Techniques: editorial message.

[BibT_eX]

[DOI]

Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

Leveraging Data Promotion for Low Power D-NUCA Caches.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

Modelling Public Administration Portals.

[BibT_eX]

[DOI]

Michele Zanda

Proceedings of the Encyclopedia of Portal Technologies and Applications (2 Volumes), 2007

MEmory performance: DEaling with applications, systems and architecture.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2007

Improving power efficiency of D-NUCA caches.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2007

Assisting e-government users with animated talking faces.

[BibT_eX]

[DOI]

Interactions, 2007

Analysis of static and dynamic energy consumption in NUCA caches: initial results.

[BibT_eX]

[DOI]

Proceedings of the 2007 workshop on MEmory performance, 2007

2006

Memory performance: dealing with applications, systems and architecture.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2006

Analysis of embedded video coder systems: a system-level approach.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2006

Embedded processors and systems: Architectural issues and solutions for emerging applications.

[BibT_eX]

[DOI]

J. Embed. Comput., 2006

Editorial message for the special track on embedded systems: applications, solutions, and techniques.

[BibT_eX]

[DOI]

François Bodin

Proceedings of the 2006 ACM Symposium on Applied Computing (SAC), 2006

2005

Optimizing instruction cache performance of embedded systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2005

Guests editor's introduction.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2005

Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2005

A cache design for high performance embedded systems.

[BibT_eX]

[DOI]

Daniele Mangano

J. Embed. Comput., 2005

An Innovative Tool to Easily Get Usable Web Sites.

[BibT_eX]

Michele Zanda

Proceedings of the WEBIST 2005, 2005

A NUCA Model for Embedded Systems Cache Design.

[BibT_eX]

[DOI]

Daniele Mangano

Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

2004

A proposal for input-sensitivity analysis of profile-driven optimizations on embedded applications.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2004

Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems.

[BibT_eX]

[DOI]

Thomas M. Conte

IEEE Micro, 2004

Speeding-up multiprocessors running DBMS workloads through coherence protocols.

[BibT_eX]

[DOI]

Int. J. High Perform. Comput. Netw., 2004

Editorial message for the special track on embedded systems: applications, solutions, and techniques.

[BibT_eX]

[DOI]

Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

2003

Fine-grain design space exploration for a cartographic SoC multiprocessor.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2003

Embedded Systems Track Editorial.

[BibT_eX]

[DOI]

Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003

2002

Performance-steered design of software architectures for embedded multicore systems.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 2002

A cache-aware program transformation technique suitable for embedded systems.

[BibT_eX]

[DOI]

Inf. Softw. Technol., 2002

Use of a CORBA/RMI gateway: characterization of communication overhead.

[BibT_eX]

[DOI]

Proceedings of the Third International Workshop on Software and Performance, 2002

Web-based training on computer architecture: the case for JCachesim.

[BibT_eX]

[DOI]

Irina Branovic

Proceedings of the 2002 workshop on Computer architecture education, 2002

Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture.

[BibT_eX]

[DOI]

Proceedings of the Web Engineering and Peer-to-Peer Computing, 2002

2001

Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2001

Behavior investigation of concurrent Java programs: an approach based on source-code instrumentation.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2001

An Object Level Transformation Technique to Improve the Performance of Embedded Applications.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2001), 2001

Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload.

[BibT_eX]

[DOI]

Proceedings of the 34th Annual Hawaii International Conference on System Sciences (HICSS-34), 2001

2000

Performance Analysis of Electronic Commerce Multiprocessor Server.

[BibT_eX]

[DOI]

Proceedings of the 33rd Annual Hawaii International Conference on System Sciences (HICSS-33), 2000

1999

PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 1999

Process Migration Effects on Memory Performance of Multiprocessor.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing, 1999

Dealing with Non-Determinism in Communications within Java Applications.

[BibT_eX]

[DOI]

Raffaele Lapadula

Proceedings of the 25th EUROMICRO '99 Conference, 1999

1998

An educational environment for designing and performance tuning of embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 1998 workshop on Computer architecture education, 1998

Analysis of Sharing Overhead in Shared Memory Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998

1997

The ChARM tool for tuning embedded systems.

[BibT_eX]

[DOI]

Marco Graziano

Francesco Lazzarini

IEEE Micro, 1997

Trace Factory: generating workloads for trace-driven simulation of shared-bus multiprocessors.

[BibT_eX]

[DOI]

IEEE Concurrency, 1997

Cache memory design for embedded systems based on program locality analysis.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997

A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997

1996

A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 22rd EUROMICRO Conference '96, 1996

1995

A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems.

[BibT_eX]

[DOI]

Luigi M. Ricciardi

IEEE Trans. Parallel Distributed Syst., 1995

A Selective Invalidation Strategy for Cache Coherence.

[BibT_eX]

[DOI]

Luigi M. Ricciardi

IEICE Trans. Inf. Syst., 1995

Graphical design of distributed applications through reusable components.

[BibT_eX]

[DOI]

IEEE Parallel Distributed Technol. Syst. Appl., 1995

Reusing sequential software in a distributed environment.

[BibT_eX]

[DOI]

Distributed Syst. Eng., 1995

Experiences in using a cache simulation tool in an advanced computer architecture course.

[BibT_eX]

[DOI]

Proceedings of the 1995 Workshop on Computer Architecture Education, 1995

Reducing coherence-related overhead in multiprocessor systems.

[BibT_eX]

[DOI]

Luigi M. Ricciardi

Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), 1995

1994

Cachesim: A Graphical Software Environment to Support the Teaching of Computer Systems with Cache Memories.

[BibT_eX]

[DOI]

Proceedings of the Software Engineering Education, 1994

1992

A process cache memory for tightly coupled multiprocessor systems.

[BibT_eX]

[DOI]

Proceedings of the 30th Annual Southeast Regional Conference, 1992

1991

RST cache memory design for a highly coupled multiprocessor system.

[BibT_eX]

[DOI]

IEEE Micro, 1991

1990

A Distributed Commit Protocol for a Multicomputer System.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1990

A new solution of coherence protocol for tightly coupled multiprocessor systems.

[BibT_eX]

[DOI]

Microprocessing and Microprogramming, 1990

1989

A protocol for resource locking and deadlock detection in a multi-user environment.

[BibT_eX]

[DOI]

Andrea Domenici

Beatrice Lazzerini

Microprocessing and Microprogramming, 1989

1988

Event-driven debugging for distributed software.

[BibT_eX]

[DOI]

Beatrice Lazzerini

Microprocess. Microsystems, 1988

1986

Multibug: Interative Debugging in Distributed Systems.

[BibT_eX]

[DOI]

Paolo Corsini

IEEE Micro, 1986

Software development tool for target systems and EPROM programmers within a Unix environment.

[BibT_eX]

[DOI]

Paolo Corsini

Microprocess. Microsystems, 1986

1985

MuTEAM: An experience in the design of robust multiprocessor systems.

[BibT_eX]

Paolo Corsini