Cosimo Antonio Prete

According to our database1, Cosimo Antonio Prete authored at least 75 papers between 1985 and 2019.

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Bibliography

2019
Algorithms for the Detection of Blob Defects in High Speed Glass Tube Production Lines.
Proceedings of the IEEE 8th International Workshop on Advances in Sensors and Interfaces, 2019

2018
Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems.
Future Generation Comp. Syst., 2018

Stock Price Forecasting Over Adaptive Timescale Using Supervised Learning and Receptive Fields.
Proceedings of the Mining Intelligence and Knowledge Exploration, 2018

2015
An architecture to integrate IEC 61131-3 systems in an IEC 61499 distributed solution.
Computers in Industry, 2015

2014
Evaluation of Leakage Reduction Alternatives for Deep Submicron Dynamic Nonuniform Cache Architecture Caches.
IEEE Trans. VLSI Syst., 2014

Social and Q&A interfaces for app download.
Inf. Process. Manage., 2014

2013
A Social-Feedback Enriched Interface for Software Download.
JOEUC, 2013

2012
A real-time configurable NURBS interpolator with bounded acceleration, jerk and chord error.
Computer-Aided Design, 2012

Integration of existing IEC 61131-3 systems in an IEC 61499 distributed solution.
Proceedings of 2012 IEEE 17th International Conference on Emerging Technologies & Factory Automation, 2012

2011
NUMA Caches.
Proceedings of the Encyclopedia of Parallel Computing, 2011

Eighth MEDEA Workshop.
Trans. HiPEAC, 2011

2010
Way adaptable D-NUCA caches.
IJHPSA, 2010

Feedback-Driven Restructuring of Multi-threaded Applications for NUCA Cache Performance in CMPs.
Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010

NURBS interpolator with confined chord error and tangential and centripetal acceleration control.
Proceedings of the International Conference on Ultra Modern Telecommunications, 2010

Re-NUCA: Boosting CMP Performance Through Block Replication.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Impact of on-chip network parameters on nuca cache performances.
IET Computers & Digital Techniques, 2009

Analysis of Performance Dependencies in NUCA-Based CMP Systems.
Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing, 2009

An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

A power-efficient migration mechanism for D-NUCA caches.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Performance Sensitivity of NUCA Caches to On-Chip Network Parameters.
Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

Special track on Embedded Systems: Applications, Solutions, and Techniques: editorial message.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

Leveraging Data Promotion for Low Power D-NUCA Caches.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Modelling Public Administration Portals.
Proceedings of the Encyclopedia of Portal Technologies and Applications (2 Volumes), 2007

MEmory performance: DEaling with applications, systems and architecture.
SIGARCH Computer Architecture News, 2007

Improving power efficiency of D-NUCA caches.
SIGARCH Computer Architecture News, 2007

Assisting e-government users with animated talking faces.
Interactions, 2007

2006
Memory performance: dealing with applications, systems and architecture.
SIGARCH Computer Architecture News, 2006

Analysis of embedded video coder systems: a system-level approach.
SIGARCH Computer Architecture News, 2006

Embedded processors and systems: Architectural issues and solutions for emerging applications.
J. Embedded Computing, 2006

2005
Optimizing instruction cache performance of embedded systems.
ACM Trans. Embedded Comput. Syst., 2005

Guests editor's introduction.
SIGARCH Computer Architecture News, 2005

Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload.
J. Parallel Distrib. Comput., 2005

A cache design for high performance embedded systems.
J. Embedded Computing, 2005

An Innovative Tool to Easily Get Usable Web Sites.
Proceedings of the WEBIST 2005, 2005

Editorial message for the special track on embedded systems: applications, solutions, and techniques.
Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), 2005

A NUCA Model for Embedded Systems Cache Design.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

2004
A proposal for input-sensitivity analysis of profile-driven optimizations on embedded applications.
SIGARCH Computer Architecture News, 2004

Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems.
IEEE Micro, 2004

Speeding-up multiprocessors running DBMS workloads through coherence protocols.
IJHPCN, 2004

Editorial message for the special track on embedded systems: applications, solutions, and techniques.
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

2003
Fine-grain design space exploration for a cartographic SoC multiprocessor.
SIGARCH Computer Architecture News, 2003

Embedded Systems Track Editorial.
Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003

2002
Performance-steered design of software architectures for embedded multicore systems.
Softw., Pract. Exper., 2002

A cache-aware program transformation technique suitable for embedded systems.
Information & Software Technology, 2002

Use of a CORBA/RMI gateway: characterization of communication overhead.
Proceedings of the Third International Workshop on Software and Performance, 2002

Web-based training on computer architecture: the case for JCachesim.
Proceedings of the 2002 workshop on Computer architecture education, 2002

Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture.
Proceedings of the Web Engineering and Peer-to-Peer Computing, 2002

2001
Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction.
SIGARCH Computer Architecture News, 2001

Behavior investigation of concurrent Java programs: an approach based on source-code instrumentation.
Future Generation Comp. Syst., 2001

An Object Level Transformation Technique to Improve the Performance of Embedded Applications.
Proceedings of the 1st IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2001), 2001

Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload.
Proceedings of the 34th Annual Hawaii International Conference on System Sciences (HICSS-34), 2001

2000
Performance Analysis of Electronic Commerce Multiprocessor Server.
Proceedings of the 33rd Annual Hawaii International Conference on System Sciences (HICSS-33), 2000

1999
PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors.
IEEE Trans. Parallel Distrib. Syst., 1999

Process Migration Effects on Memory Performance of Multiprocessor.
Proceedings of the High Performance Computing, 1999

Dealing with Non-Determinism in Communications within Java Applications.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

1998
An educational environment for designing and performance tuning of embedded systems.
Proceedings of the 1998 workshop on Computer architecture education, 1998

Analysis of Sharing Overhead in Shared Memory Multiprocessors.
Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998

1997
The ChARM tool for tuning embedded systems.
IEEE Micro, 1997

Trace Factory: generating workloads for trace-driven simulation of shared-bus multiprocessors.
IEEE Concurrency, 1997

Cache memory design for embedded systems based on program locality analysis.
Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997

A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors.
Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997

1996
A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors.
Proceedings of the 22rd EUROMICRO Conference '96, 1996

1995
A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems.
IEEE Trans. Parallel Distrib. Syst., 1995

A Selective Invalidation Strategy for Cache Coherence.
IEICE Transactions, 1995

Graphical design of distributed applications through reusable components.
IEEE P&DT, 1995

Reusing sequential software in a distributed environment.
Distributed Systems Engineering, 1995

Reducing coherence-related overhead in multiprocessor systems.
Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), 1995

1994
Cachesim: A Graphical Software Environment to Support the Teaching of Computer Systems with Cache Memories.
Proceedings of the Software Engineering Education, 1994

1992
A process cache memory for tightly coupled multiprocessor systems.
Proceedings of the 30th Annual Southeast Regional Conference, 1992

1991
RST cache memory design for a highly coupled multiprocessor system.
IEEE Micro, 1991

1990
A Distributed Commit Protocol for a Multicomputer System.
IEEE Trans. Computers, 1990

1988
Event-driven debugging for distributed software.
Microprocessors and Microsystems - Embedded Hardware Design, 1988

1986
Multibug: Interative Debugging in Distributed Systems.
IEEE Micro, 1986

Software development tool for target systems and EPROM programmers within a Unix environment.
Microprocessors and Microsystems - Embedded Hardware Design, 1986

1985
MuTEAM: An experience in the design of robust multiprocessor systems.
Comput. Syst. Sci. Eng., 1985


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