Pierfrancesco Foglia

According to our database1, Pierfrancesco Foglia authored at least 47 papers between 1998 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2019
Algorithms for the Detection of Blob Defects in High Speed Glass Tube Production Lines.
Proceedings of the IEEE 8th International Workshop on Advances in Sensors and Interfaces, 2019

2018
Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems.
Future Gener. Comput. Syst., 2018

Stock Price Forecasting Over Adaptive Timescale Using Supervised Learning and Receptive Fields.
Proceedings of the Mining Intelligence and Knowledge Exploration, 2018

2015
An architecture to integrate IEC 61131-3 systems in an IEC 61499 distributed solution.
Comput. Ind., 2015

2014
Evaluation of Leakage Reduction Alternatives for Deep Submicron Dynamic Nonuniform Cache Architecture Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A workload independent energy reduction strategy for D-NUCA caches.
J. Supercomput., 2014

Exploiting replication to improve performances of NUCA-based CMP systems.
ACM Trans. Embed. Comput. Syst., 2014

Social and Q&A interfaces for app download.
Inf. Process. Manag., 2014

Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant Caches.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

2013
A Social-Feedback Enriched Interface for Software Download.
J. Organ. End User Comput., 2013

2012
A real-time configurable NURBS interpolator with bounded acceleration, jerk and chord error.
Comput. Aided Des., 2012

Integration of existing IEC 61131-3 systems in an IEC 61499 distributed solution.
Proceedings of 2012 IEEE 17th International Conference on Emerging Technologies & Factory Automation, 2012

2011
NUMA Caches.
Proceedings of the Encyclopedia of Parallel Computing, 2011

Eighth MEDEA Workshop.
Trans. High Perform. Embed. Archit. Compil., 2011

Energy Behaviour of NUCA Caches in CMPs.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Way adaptable D-NUCA caches.
Int. J. High Perform. Syst. Archit., 2010

Feedback-Driven Restructuring of Multi-threaded Applications for NUCA Cache Performance in CMPs.
Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010

NURBS interpolator with confined chord error and tangential and centripetal acceleration control.
Proceedings of the International Conference on Ultra Modern Telecommunications, 2010

Re-NUCA: Boosting CMP Performance Through Block Replication.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Impact of on-chip network parameters on nuca cache performances.
IET Comput. Digit. Tech., 2009

Analysis of Performance Dependencies in NUCA-Based CMP Systems.
Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing, 2009

An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

A power-efficient migration mechanism for D-NUCA caches.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Performance Sensitivity of NUCA Caches to On-Chip Network Parameters.
Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

Leveraging Data Promotion for Low Power D-NUCA Caches.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Modelling Public Administration Portals.
Proceedings of the Encyclopedia of Portal Technologies and Applications (2 Volumes), 2007

MEmory performance: DEaling with applications, systems and architecture.
SIGARCH Comput. Archit. News, 2007

Improving power efficiency of D-NUCA caches.
SIGARCH Comput. Archit. News, 2007

Assisting e-government users with animated talking faces.
Interactions, 2007

Reconfigurable split data caches: a novel scheme for embedded systems.
Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), 2007

2006
Memory performance: dealing with applications, systems and architecture.
SIGARCH Comput. Archit. News, 2006

Analysis of embedded video coder systems: a system-level approach.
SIGARCH Comput. Archit. News, 2006

Embedded processors and systems: Architectural issues and solutions for emerging applications.
J. Embed. Comput., 2006

2005
Guests editor's introduction.
SIGARCH Comput. Archit. News, 2005

Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload.
J. Parallel Distributed Comput., 2005

A cache design for high performance embedded systems.
J. Embed. Comput., 2005

An Innovative Tool to Easily Get Usable Web Sites.
Proceedings of the WEBIST 2005, 2005

A NUCA Model for Embedded Systems Cache Design.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

2004
Speeding-up multiprocessors running DBMS workloads through coherence protocols.
Int. J. High Perform. Comput. Netw., 2004

2003
Fine-grain design space exploration for a cartographic SoC multiprocessor.
SIGARCH Comput. Archit. News, 2003

2002
Use of a CORBA/RMI gateway: characterization of communication overhead.
Proceedings of the Third International Workshop on Software and Performance, 2002

Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture.
Proceedings of the Web Engineering and Peer-to-Peer Computing, 2002

2001
Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload.
Proceedings of the 34th Annual Hawaii International Conference on System Sciences (HICSS-34), 2001

2000
Performance Analysis of Electronic Commerce Multiprocessor Server.
Proceedings of the 33rd Annual Hawaii International Conference on System Sciences (HICSS-33), 2000

1999
Process Migration Effects on Memory Performance of Multiprocessor.
Proceedings of the High Performance Computing, 1999

1998
MPEG video traffic on a MetaRing network: complexity reduction of a 'worst-case' model for bandwidth allocation analysis.
Comput. Commun., 1998

Analysis of Sharing Overhead in Shared Memory Multiprocessors.
Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998


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