Alexander Zaslavsky

Orcid: 0000-0002-5240-0271

According to our database¹, Alexander Zaslavsky authored at least 15 papers between 2005 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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Bibliography

2024

Optimization of Discrete Parameters Using the Adaptive Gradient Method and Directed Evolution.

[BibT_eX]

[DOI]

Andrei Beinarovich

Sergey Stepanov

Alexander Zaslavsky

CoRR, 2024

2018

A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2016

Design of Error-Resilient Logic Gates with Reinforcement Using Implications.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

A fast simulator for the analysis of sub-threshold thermal noise transients.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2012

A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Z<sup>2</sup>-FET used as 1-transistor high-speed DRAM.

[BibT_eX]

[DOI]

Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2010

Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2007

Designing Nanoscale Logic Circuits Based on Markov Random Fields.

[BibT_eX]

[DOI]

J. Electron. Test., 2007

Thermally-induced soft errors in nanoscale CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits.

[BibT_eX]

[DOI]

IEEE Micro, 2006

Optimizing noise-immune nanoscale circuits using principles of Markov random fields.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Designing MRF based error correcting circuits for memory elements.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Designing logic circuits for probabilistic computation in the presence of noise.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Alexander Zaslavsky

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