R. Iris Bahar

According to our database1, R. Iris Bahar authored at least 117 papers between 1994 and 2019.

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Bibliography

2019
Automated High-Level Generation of Low-Power Approximate Computing Circuits.
IEEE Trans. Emerging Topics Comput., 2019

Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack.
J. Electronic Testing, 2019

Conference Reports: Recap of the 37th Edition of the International Conference on Computer-Aided Design (ICCAD 2018).
IEEE Design & Test, 2019

Special Session: Does Approximation Make Testing Harder (or Easier)?
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation.
Proceedings of the 31st ACM on Symposium on Parallelism in Algorithms and Architectures, 2019

Attacking memory-hard scrypt with near-data-processing.
Proceedings of the International Symposium on Memory Systems, 2019

GRIP: Generative Robust Inference and Perception for Semantic Robot Manipulation in Adversarial Environments.
Proceedings of the 2019 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2019

Test Architecture for Fine Grained Capture Power Reduction.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Energy-efficient and Sustainable Computing across the Hardware/Software Stack.
Proceedings of the Tenth International Green and Sustainable Computing Conference, 2019

IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Towards the Simulation Based Design and Validation of Mobile Robotic Cyber-Physical Systems.
J. Low Power Electronics, 2018

Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures.
International Journal of Parallel Programming, 2018

Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD).
IEEE Design & Test, 2018

Robust object estimation using generative-discriminative inference for secure robotics applications.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency.
ACM Trans. Embedded Comput. Syst., 2017

A Research Tool for the Power and Performance Analysis of Sensor-Based Mobile Robots.
Proceedings of the New Generation of CAS, 2017

Evaluating critical bits in arithmetic operations due to timing violations.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

Understanding the impact of precision quantization on the accuracy and energy of neural networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Using Existing Reconfigurable Logic in 3D Die Stacks for Test.
Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016

Design of Error-Resilient Logic Gates with Reinforcement Using Implications.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Hardware acceleration of feature detection and description algorithms on low-power embedded platforms.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

A low-power dynamic divider for approximate applications.
Proceedings of the 53rd Annual Design Automation Conference, 2016

A fast simulator for the analysis of sub-threshold thermal noise transients.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Runtime configurable deep neural networks for energy-accuracy trade-off.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems.
Proceedings of the 2016 International Conference on Compilers, 2016

2015
Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems.
ACM Trans. Design Autom. Electr. Syst., 2015

Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems.
ACM Trans. Embedded Comput. Syst., 2015

Repairing a 3-D Die-Stack Using Available Programmable Logic.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Message from the program co-chairs.
Proceedings of the 10th IEEE International Conference on Networking, 2015

DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators.
TRETS, 2014

Speculative synchronization for coherence-free embedded NUMA architectures.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

ABACUS: A technique for automated behavioral synthesis of approximate computing circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
"Scaling" the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Flexible data allocation for scratch-pad memories to reduce NBTI effects.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

Built-in Self-Repair in a 3D die stack using programmable logic.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012
Using implications to choose tests through suspect fault identification.
ACM Trans. Design Autom. Electr. Syst., 2012

NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems.
J. Electronic Testing, 2012

A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

High Performance Parallel JPEG2000 Streaming Decoder Using GPGPU-CPU Heterogeneous System.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems.
J. Electronic Testing, 2011

Enhancing online error detection through area-efficient multi-site implications.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

A novel parallel Tier-1 coder for JPEG2000 using GPUs.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis.
Proceedings of the 16th European Test Symposium, 2011

SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010
Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence.
IEEE Trans. VLSI Syst., 2010

A Cost Effective Approach for Online Error Detection Using Invariant Relationships.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Dual-Vt assignment policies in ITD-aware synthesis.
Microelectronics Journal, 2010

Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems.
J. Parallel Distrib. Comput., 2010

Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010

Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Improving the testability and reliability of sequential circuits with invariant logic.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
Introduction to special section: Best of NANOARCH 2008.
JETC, 2009

AutoRex: An automated post-silicon clock tuning tool.
Proceedings of the 2009 IEEE International Test Conference, 2009

Reducing the leakage and timing variability of 2D ICcs using 3D ICs.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Compacting test vector sets via strategic use of implications.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Energy-optimal synchronization primitives for single-chip multi-processors.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

High-performance, cost-effective heterogeneous 3D FPGA architectures.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Detecting errors using multi-cycle invariance information.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Thermal-Aware Design Techniques for Nanometer CMOS Circuits.
J. Low Power Electronics, 2008

Parametric yield management for 3D ICs: Models and strategies for improvement.
JETC, 2008

Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies.
JETC, 2008

Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Using Implications for Online Error Detection.
Proceedings of the 2008 IEEE International Test Conference, 2008

Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Energy efficient synchronization techniques for embedded architectures.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Temperature-insensitive synthesis using multi-vt libraries.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
A hardware/software framework for supporting transactional memory in a MPSoC environment.
SIGARCH Computer Architecture News, 2007

Designing Nanoscale Logic Circuits Based on Markov Random Fields.
J. Electronic Testing, 2007

Architectures for Silicon Nanoelectronics and Beyond.
IEEE Computer, 2007

Thermally-induced soft errors in nanoscale CMOS circuits.
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

Strategies for improving the parametric yield and profits of 3D ICs.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Accurate timing analysis using SAT and pattern-dependent delay models.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Timing analysis for full-custom circuits using symbolic DC formulations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits.
IEEE Micro, 2006

Energy implications of multiprocessor synchronization.
Proceedings of the SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30, 2006

Trends and Future Directions in Nano Structure Based Computing and Fabrication.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Optimizing noise-immune nanoscale circuits using principles of Markov random fields.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Designing MRF based error correcting circuits for memory elements.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale.
IEEE Design & Test of Computers, 2005

Energy reduction in multiprocessor systems using transactional memory.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Designing logic circuits for probabilistic computation in the presence of noise.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Effects of speculation on performance and issue queue design.
IEEE Trans. VLSI Syst., 2004

A low-power in-order/out-of-order issue queue.
TACO, 2004

Fetch Halting on Critical Load Misses.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

RESTA: a robust and extendable symbolic timing analysis tool.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003
A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A Probabilistic-Based Design Methodology for Nanoscale Computation.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Power-aware issue queue design for speculative instructions.
Proceedings of the 40th Design Automation Conference, 2003

Combining Software and Hardware Monitoring for Improved Power and Performance Tuning.
Proceedings of the 7th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-7 2003), 2003

2002
Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

2001
Power and energy reduction via pipeline balancing.
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

2000
Power optimization of technology-dependent circuits based on symbolic computation of logic implications.
ACM Trans. Design Autom. Electr. Syst., 2000

Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors.
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

1999
A comparison of software code reordering and victim buffers.
SIGARCH Computer Architecture News, 1999

The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency.
Proceedings of the IEEE International Conference On Computer Design, 1999

1998
Power and performance tradeoffs using various caching strategies.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

1997
Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Algebraic Decision Diagrams and Their Applications.
Formal Methods in System Design, 1997

1996
Symbolic computation of logic implications for technology-dependent low-power synthesis.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995
CMOS dynamic power estimation based on collapsible current source transistor modeling.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Boolean techniques for low power driven re-synthesis.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Computing the Maximum Power Cycles of a Sequential Circuit.
Proceedings of the 32st Conference on Design Automation, 1995

1994
A symbolic method to reduce power consumption of circuits containing false paths.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

An ADD-based algorithm for shortest path back-tracing of large graphs.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Timing Analysis of Combinational Circuits using ADD's.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994


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