Alexandre da Costa Sena

Orcid: 0000-0002-8931-9397

According to our database1, Alexandre da Costa Sena authored at least 36 papers between 2001 and 2022.

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Bibliography

2022
On Using Consistency Consistently in Multiple Sequence Alignments.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

2021
Enabling heterogeneous ray-tracing acceleration in edge/cloud architectures.
Concurr. Comput. Pract. Exp., 2021

A Computational Analysis of the Hopmoc Method Applied to the 2-D Advection-Diffusion and Burgers Equations.
Proceedings of the Computational Science and Its Applications - ICCSA 2021, 2021

An Efficient Vectorized Auction Algorithm for Many-Core and Multicore Architectures.
Proceedings of the High Performance Computing - 8th Latin American Conference, 2021

2020
A Case Study for Implementing a Laboratory Information Management System for HLA Typing.
Proceedings of the 2020 IEEE International Conference on Software Architecture Companion, 2020

A Convergence Analysis of a Multistep Method Applied to an Advection-Diffusion Equation in 1-D.
Proceedings of the Computational Science and Its Applications - ICCSA 2020, 2020

2019
An efficient pathfinding system in FPGA for edge/fog computing.
Int. J. Grid Util. Comput., 2019

A network coding protocol for wireless sensor fog computing.
Int. J. Grid Util. Comput., 2019

A dataflow runtime environment and static scheduler for edge, fog and in-situ computing.
Int. J. Grid Util. Comput., 2019

DF-DTM: Dynamic Task Memoization and reuse in dataflow.
Concurr. Comput. Pract. Exp., 2019

DTM@GPU: Characterizing and evaluating trace redundancy in GPU.
Concurr. Comput. Pract. Exp., 2019

On the parallelization of Hirschberg's algorithm for multi-core and many-core systems.
Concurr. Comput. Pract. Exp., 2019

Numerical Simulations of the 1-D Modified Burgers Equation.
Proceedings of the 2019 Winter Simulation Conference, 2019

A Re-Configurable Ray-Triangle Vector Accelerator for Emerging Fog Architectures.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

2018
Efficient A* Co-processor for Reconfigurable Gaming Devices.
Proceedings of the 17th Brazilian Symposium on Computer Games and Digital Entertainment, SBGames 2018, Foz do Iguaçu, Brazil, October 29, 2018

A Malleable Vectorized Auction Algorithm for Modern Multicore Architectures.
Proceedings of the 20th IEEE International Conference on High Performance Computing and Communications; 16th IEEE International Conference on Smart City; 4th IEEE International Conference on Data Science and Systems, 2018

2017
Optimising loops in dynamic dataflow.
IET Circuits Devices Syst., 2017

Efficient Pathfinding Co-Processors for FPGAs.
Proceedings of the 2017 International Symposium on Computer Architecture and High Performance Computing Workshops, 2017

A Dataflow Implementation of Region Growing Method for Cracks Segmentation.
Proceedings of the 2017 International Symposium on Computer Architecture and High Performance Computing Workshops, 2017

A Communication Protocol for Fog Computing Based on Network Coding Applied to Wireless Sensors.
Proceedings of the 2017 International Symposium on Computer Architecture and High Performance Computing Workshops, 2017

Towards a Dataflow Runtime Environment for Edge, Fog and In-Situ Computing.
Proceedings of the 2017 International Symposium on Computer Architecture and High Performance Computing Workshops, 2017

2016
Task Scheduling in Sucuri Dataflow Library.
Proceedings of the 2016 International Symposium on Computer Architecture and High Performance Computing Workshops, 2016

A Hybrid Parallel Algorithm for the Auction Algorithm in Multicore Systems.
Proceedings of the 2016 International Symposium on Computer Architecture and High Performance Computing Workshops, 2016

2015
Graph Templates for Dataflow Programming.
Proceedings of the 2015 International Symposium on Computer Architecture and High Performance Computing Workshops, 2015

2014
Dataflow Virtual Machine Profiling.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshop, 2014

2013
Improving Memory Hierarchy Utilisation for Stencil Computations on Multicore Machines.
CoRR, 2013

Autonomic Malleability in Iterative MPI Applications.
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

2011
An Approach to Optimise the Execution of RTM Algorithm in Multicore Machines.
Proceedings of the IEEE 7th International Conference on E-Science, 2011

2009
On the Feasibility of Dynamically Scheduling DAG Applications on Shared Heterogeneous Systems.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009

2008
Autonomic application management for large scale MPI programs.
Int. J. High Perform. Comput. Netw., 2008

EasyGrid Enabling of Iterative Tightly-Coupled Parallel MPI Applications.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008

2007
Distributed and dynamic self-scheduling of parallel MPI Grid applications.
Concurr. Comput. Pract. Exp., 2007

On the Advantages of an Alternative MPI Execution Model for Grids.
Proceedings of the Seventh IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2007), 2007

2005
Managing the Execution of Large Scale MPI Applications on Computational Grids.
Proceedings of the 17th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2005), 2005

Efficient hierarchical self-scheduling for MPI applications executing in computational Grids.
Proceedings of the 3rd international workshop on Middleware for grid computing, 2005

2001
Uma Abordagem para Acesso Dinâmico a Objetos Distribuídos em lingoal.
Proceedings of the 1st Ibero-American Symposium on Software Engineering and Knowledge Engineering (JIISIC'01), 2001


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