Alfonso Mascareñas González

According to our database, Alfonso Mascareñas González authored at least 10 papers between 2021 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

Validating compositional-based models of core memory hierarchies through MPSoC events.

Alfonso Mascareñas González, Frédéric Boniol, Camille Coquand, Benjamin Lesage, Claire Pagetti

J. Syst. Archit., 2026

2025

Towards a validated core memory model through (MP)SoC events.

Alfonso Mascareñas González, Frédéric Boniol, Benjamin Lesage, Claire Pagetti

Proceedings of the 27th IEEE International Symposium on Real-Time Distributed Computing, 2025

Analysis of Modern Memory Management Unit Functioning for Critical Systems.

Alfonso Mascareñas González, Youcef Bouchebaba

Proceedings of the 28th Euromicro Conference on Digital System Design, 2025

2024

Towards the Certification of Hybrid Architectures: Analysing Interference on Hardware Accelerators through PML.

Benjamin Lesage, Frédéric Boniol, Kevin Delmas, Adrien Gauffriau, Alfonso Mascareñas González, Claire Pagetti

CoRR, 2024

Optimal Real-Time Task Allocation in Heteregeneous Multi-Core Embedded Systems.

David Doose, Youcef Bouchebaba, Alfonso Mascareñas González

Proceedings of the 30th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2024

2023

Exploring iGPU Memory Interference Response to L2 Cache Locking.

Alfonso Mascareñas González, Jean-Baptiste Chaudron, Régine Leconte, Youcef Bouchebaba, David Doose

Proceedings of the 21th International Workshop on Worst-Case Execution Time Analysis, 2023

Exploring Segnet Architectures for iGPU Embedded Devices.

Jean-Baptiste Chaudron, Alfonso Mascareñas González

Proceedings of the 15th International Joint Conference on Computational Intelligence, 2023

2022

Task and Memory Mapping Optimization for SDRAM Interference Minimization on Heterogeneous MPSoCs.

Alfonso Mascareñas González, Jean-Baptiste Chaudron, Frédéric Boniol, Youcef Bouchebaba, Jean-Loup Bussenot

Proceedings of the 27th IEEE International Conference on Emerging Technologies and Factory Automation, 2022

Towards an efficient cost function equation for DDR SDRAM interference analysis on heterogeneous MPSoCs.

Alfonso Mascareñas González, Jean-Baptiste Chaudron, Frédéric Boniol, Youcef Bouchebaba, Jean-Loup Bussenot

Proceedings of the 26th IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications, 2022

2021

Heterogeneous multicore SDRAM interference analysis.

Alfonso Mascareñas González, Frédéric Boniol, Youcef Bouchebaba, Jean-Loup Bussenot, Jean-Baptiste Chaudron

Proceedings of the RTNS'2021: 29th International Conference on Real-Time Networks and Systems, 2021