Youcef Bouchebaba

According to our database1, Youcef Bouchebaba authored at least 25 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
Exploring iGPU Memory Interference Response to L2 Cache Locking.
Proceedings of the 21th International Workshop on Worst-Case Execution Time Analysis, 2023

2022
Task and Memory Mapping Optimization for SDRAM Interference Minimization on Heterogeneous MPSoCs.
Proceedings of the 27th IEEE International Conference on Emerging Technologies and Factory Automation, 2022

Towards an efficient cost function equation for DDR SDRAM interference analysis on heterogeneous MPSoCs.
Proceedings of the 26th IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications, 2022

2021
Heterogeneous multicore SDRAM interference analysis.
Proceedings of the RTNS'2021: 29th International Conference on Real-Time Networks and Systems, 2021

2019
Parallel Applications Mapping onto Network on Chip Based on Heterogeneous MPSoCs Using Hybrid Algorithms.
Int. J. Distributed Syst. Technol., 2019

Statistical Analysis for Shared Resources Effects with Multi-Core Real-Time Systems.
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

2016
Network on Chip and Parallel Computing in Embedded Systems.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

2014
Fast and accurate implementation of Canny edge detector on embedded many-core platform.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

2012
Integrating Memory Optimization with Mapping Algorithms for Multi-Processors System-on-Chip.
ACM Trans. Embed. Comput. Syst., 2012

MpAssign: a framework for solving the many-core platform mapping problem.
Softw. Pract. Exp., 2012

2010
Combining mapping and partitioning exploration for NoC-based embedded systems.
J. Syst. Archit., 2010

Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chip.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

MpAssign: A framework for solving the many-core platform mapping problem.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

2009
Multiprocessor, Multithreading and Memory Optimization for On-Chip Multimedia Applications.
J. Signal Process. Syst., 2009

Optimizing Configuration and Application Mapping for MPSoC Architectures.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2007
Buffer and Register Allocation for Memory Space Optimization.
J. VLSI Signal Process., 2007

MPSoC memory optimization using program transformation.
ACM Trans. Design Autom. Electr. Syst., 2007

MPSoC memory optimization for digital camera applications.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

System level assessment of an optical NoC in an MPSoC platform.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Two-level tiling for MPSoC architecture.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Application-Level Memory Optimization for MPSoC.
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

Buffer and register allocation for memory space optimization.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2002
Pavage pour une séquence de nids de boucles.
Tech. Sci. Informatiques, 2002

Tiling and Memory Reuse for Sequences of Nested Loops.
Proceedings of the Euro-Par 2002, 2002

1999
A New Genetic Algorithm for the Optimal Communication Spanning Tree Problem.
Proceedings of the Artificial Evolution, 4th European Conference, 1999


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