Amey M. Kulkarni

According to our database1, Amey M. Kulkarni authored at least 18 papers between 2014 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
SENSE: Sketching Framework for Big Data Acceleration on Low Power Embedded Cores.
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019

2018
Accelerating Convolutional Neural Network With FFT on Embedded Hardware.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Low Overhead CS-Based Heterogeneous Framework for Big Data Acceleration.
ACM Trans. Embed. Comput. Syst., 2018

2017
Low Overhead Architectures for OMP Compressive Sensing Reconstruction Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

PACENet: Energy efficient acceleration for convolutional network on embedded platform.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Accelerating convolutional neural network with FFT on tiny cores.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A Scalable FPGA-Based Accelerator for High-Throughput MCMC Algorithms.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

LESS: Big data sketching and Encryption on low power platform.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Real-Time Anomaly Detection Framework for Many-Core Router through Machine-Learning Techniques.
ACM J. Emerg. Technol. Comput. Syst., 2016

SVM-based real-time hardware Trojan detection for many-core platform.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Sketching-based high-performance biomedical big data processing accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Adaptive real-time Trojan detection framework through machine learning.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Low Energy Sketching Engines on Many-Core Platform for Big Data Acceleration.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

CS-Based Secured Big Data Processing on FPGA.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015
Accelerating compressive sensing reconstruction OMP algorithm with CPU, GPU, FPGA and domain specific many-core.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Utilizing deep neural nets for an embedded ECG-based biometric authentication system.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014
Energy-efficient mapping of biomedical applications on domain-specific accelerator under process variation.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

A parallel and reconfigurable architecture for efficient OMP compressive sensing reconstruction.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014


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