Abbas Rahimi
Orcid: 0000-0003-3141-4970
According to our database1,
Abbas Rahimi
authored at least 110 papers
between 2010 and 2024.
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Bibliography
2024
CoRR, 2024
Probabilistic Abduction for Visual Abstract Reasoning via Learning Rules in Vector-symbolic Architectures.
CoRR, 2024
2023
Generalized Key-Value Memory to Flexibly Adjust Redundancy in Memory-Augmented Networks.
IEEE Trans. Neural Networks Learn. Syst., December, 2023
Nat. Mac. Intell., April, 2023
WHYPE: A Scale-Out Architecture With Wireless Over-the-Air Majority for Scalable In-Memory Hyperdimensional Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
Raw data related to In-memory factorization of holographic perceptual representations.
Dataset, February, 2023
Proceedings of the Compendium of Neurosymbolic Artificial Intelligence, 2023
A Survey on Hyperdimensional Computing aka Vector Symbolic Architectures, Part II: Applications, Cognitive Models, and Challenges.
ACM Comput. Surv., 2023
A Survey on Hyperdimensional Computing aka Vector Symbolic Architectures, Part I: Models and Data Transformations.
ACM Comput. Surv., 2023
TCNCA: Temporal Convolution Network with Chunked Attention for Scalable Sequence Processing.
CoRR, 2023
Model-Driven Engineering for Artificial Intelligence - A Systematic Literature Review.
CoRR, 2023
MIMONets: Multiple-Input-Multiple-Output Neural Networks Exploiting Computation in Superposition.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
Proceedings of the 17th International Workshop on Neural-Symbolic Learning and Reasoning, 2023
Proceedings of the 17th International Workshop on Neural-Symbolic Learning and Reasoning, 2023
VSA-based Positional Encoding Can Replace Recurrent Networks in Emergent Symbol Binding.
Proceedings of the 17th International Workshop on Neural-Symbolic Learning and Reasoning, 2023
Proceedings of the ACM/IEEE International Conference on Model Driven Engineering Languages and Systems, 2023
2022
Proc. IEEE, 2022
Proceedings of the International Joint Conference on Neural Networks, 2022
In-memory Realization of In-situ Few-shot Continual Learning with a Dynamically Evolving Explicit Memory.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022
2021
An Ensemble of Hyperdimensional Classifiers: Hardware-Friendly Short-Latency Seizure Detection With Automatic iEEG Electrode Selection.
IEEE J. Biomed. Health Informatics, 2021
Energy Efficient In-Memory Hyperdimensional Encoding for Spatio-Temporal Signal Processing.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 5 μW Standard Cell Memory-Based Configurable Hyperdimensional Computing Accelerator for Always-on Smart Sensing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Computers, 2021
ERCIM News, 2021
CoRR, 2021
Near-channel classifier: symbiotic communication and classification in high-dimensional space.
Brain Informatics, 2021
Assessing Robustness of Hyperdimensional Computing Against Errors in Associative Memory : (Invited Paper).
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021
Real-time Language Recognition using Hyperdimensional Computing on Phase-change Memory Array.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Hyperdimensional Computing With Local Binary Patterns: One-Shot Learning of Seizure Onset and Identification of Ictogenic Brain Regions Using Short-Time iEEG Recordings.
IEEE Trans. Biomed. Eng., 2020
Neural Comput. Appl., 2020
Hyperdimensional Computing for Blind and One-Shot Classification of EEG Error-Related Potentials.
Mob. Networks Appl., 2020
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
Proceedings of the Wireless Mobile Communication and Healthcare, 2020
Integrating event-based dynamic vision sensors with sparse hyperdimensional computing: a low-power accelerator with online learning capability.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Compressing Subject-specific Brain-Computer Interface Models into One Model by Superposition in Hyperdimensional Space.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Evolvable Hyperdimensional Computing: Unsupervised Regeneration of Associative Memory to Recover Faulty Components.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
Binary Models for Motor-Imagery Brain-Computer Interfaces: Sparse Random Projection and Binarized SVM.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
IEEE Trans. Emerg. Top. Comput., 2019
Online Learning and Classification of EMG-Based Gestures on a Parallel Ultra-Low Power Platform Using Hyperdimensional Computing.
IEEE Trans. Biomed. Circuits Syst., 2019
Efficient Biosignal Processing Using Hyperdimensional Computing: Network Templates for Combined Learning and Classification of ExG Signals.
Proc. IEEE, 2019
Hardware Optimizations of Dense Binary Hyperdimensional Computing: Rematerialization of Hypervectors, Binarized Bundling, and Combinational Associative Memory.
ACM J. Emerg. Technol. Comput. Syst., 2019
CoRR, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Laelaps: An Energy-Efficient Seizure Detection Algorithm from Long-term Human iEEG Recordings without False Alarms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Analysis of Contraction Effort Level in EMG-Based Gesture Recognition Using Hyperdimensional Computing.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
Hyperdimensional Computing-based Multimodality Emotion Recognition with Physiological Signals.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
Classification and Recall With Binary Hyperdimensional Computing: Tradeoffs in Choice of Density and Mapping Characteristics.
IEEE Trans. Neural Networks Learn. Syst., 2018
IEEE Trans. Multi Scale Comput. Syst., 2018
CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units.
IEEE Trans. Computers, 2018
Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration.
IEEE J. Solid State Circuits, 2018
Exploring Embedding Methods in Binary Hyperdimensional Computing: A Case Study for Motor-Imagery based Brain-Computer Interfaces.
CoRR, 2018
Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
An EMG Gesture Recognition System with Flexible High-Density Sensors and Brain-Inspired High-Dimensional Classifier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Fast and Accurate Multiclass Inference for MI-BCIs Using Large Multiscale Temporal and Spectral Features.
Proceedings of the 26th European Signal Processing Conference, 2018
PULP-HD: accelerating brain-inspired high-dimensional computing on a parallel ultra-low power platform.
Proceedings of the 55th Annual Design Automation Conference, 2018
One-shot Learning for iEEG Seizure Detection Using End-to-end Binary Operations: Local Binary Patterns with Hyperdimensional Computing.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
Proceedings of the 2018 IEEE EMBS International Conference on Biomedical & Health Informatics, 2018
2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Des. Test, 2017
CoRR, 2017
Proceedings of the 7th IEEE International Workshop on Advances in Sensors and Interfaces, 2017
Proceedings of the IEEE International Conference on Rebooting Computing, 2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
SLoT: A supervised learning model to predict dynamic timing errors of functional units.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to Software.
Proc. IEEE, 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
IEEE Des. Test, 2016
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016
A Robust and Energy-Efficient Classifier Using Brain-Inspired Hyperdimensional Computing.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
ACAM: Approximate Computing Based on Adaptive Associative Memory with Online Learning.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Hyperdimensional biosignal processing: A case study for EMG-based hand gesture recognition.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Grater: An approximation workflow for exploiting data-level parallelism in FPGA acceleration.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Resistive Bloom filters: From approximate membership to approximate computing with bounded errors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
From Variability-Tolerance to Approximate Computing in Parallel Computing Architectures.
PhD thesis, 2015
it Inf. Technol., 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Task scheduling strategies to mitigate hardware variability in embedded shared memory clusters.
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
IEEE Trans. Computers, 2014
Improving Resilience to Timing Errors by Exposing Variability Effects to Software in Tightly-Coupled Processor Clusters.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
Energy-efficient mapping of biomedical applications on domain-specific accelerator under process variation.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Energy-Efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-Based Computing.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Spatial Memoization: Concurrent Instruction Reuse to Correct Timing Errors in SIMD Architectures.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Hierarchically focused guardbanding: an adaptive approach to mitigate PVT variations and aging.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
2012
Procedure hopping: a low overhead solution to mitigate variability in shared-L1 processor clusters.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Analysis of instruction-level vulnerability to dynamic voltage and temperature variations.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Microelectron. J., 2011
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters.
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010