Abbas Rahimi

According to our database1, Abbas Rahimi authored at least 68 papers between 2010 and 2020.

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Bibliography

2020
Hyperdimensional Computing With Local Binary Patterns: One-Shot Learning of Seizure Onset and Identification of Ictogenic Brain Regions Using Short-Time iEEG Recordings.
IEEE Trans. Biomed. Engineering, 2020

2019
Resistive CAM Acceleration for Tunable Approximate Computing.
IEEE Trans. Emerging Topics Comput., 2019

Online Learning and Classification of EMG-Based Gestures on a Parallel Ultra-Low Power Platform Using Hyperdimensional Computing.
IEEE Trans. Biomed. Circuits and Systems, 2019

Efficient Biosignal Processing Using Hyperdimensional Computing: Network Templates for Combined Learning and Classification of ExG Signals.
Proceedings of the IEEE, 2019

Hardware Optimizations of Dense Binary Hyperdimensional Computing: Rematerialization of Hypervectors, Binarized Bundling, and Combinational Associative Memory.
JETC, 2019

In-memory hyperdimensional computing.
CoRR, 2019

Adaptive EMG-based hand gesture recognition using hyperdimensional computing.
CoRR, 2019

Applications of Computation-In-Memory Architectures based on Memristive Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Laelaps: An Energy-Efficient Seizure Detection Algorithm from Long-term Human iEEG Recordings without False Alarms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Analysis of Contraction Effort Level in EMG-Based Gesture Recognition Using Hyperdimensional Computing.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

Hyperdimensional Computing-based Multimodality Emotion Recognition with Physiological Signals.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
Classification and Recall With Binary Hyperdimensional Computing: Tradeoffs in Choice of Density and Mapping Characteristics.
IEEE Trans. Neural Netw. Learning Syst., 2018

Multi-Stage Tunable Approximate Search in Resistive Associative Memory.
IEEE Trans. Multi-Scale Computing Systems, 2018

CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units.
IEEE Trans. Computers, 2018

Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration.
J. Solid-State Circuits, 2018

Exploring Embedding Methods in Binary Hyperdimensional Computing: A Case Study for Motor-Imagery based Brain-Computer Interfaces.
CoRR, 2018

Hyperdimensional Computing Nanosystem.
CoRR, 2018

Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

An EMG Gesture Recognition System with Flexible High-Density Sensors and Brain-Inspired High-Dimensional Classifier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An 826 MOPS, 210uW/MHz Unum ALU in 65 nm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Fast and Accurate Multiclass Inference for MI-BCIs Using Large Multiscale Temporal and Spectral Features.
Proceedings of the 26th European Signal Processing Conference, 2018

PULP-HD: accelerating brain-inspired high-dimensional computing on a parallel ultra-low power platform.
Proceedings of the 55th Annual Design Automation Conference, 2018

One-shot Learning for iEEG Seizure Detection Using End-to-end Binary Operations: Local Binary Patterns with Hyperdimensional Computing.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

HDNA: Energy-efficient DNA sequencing using hyperdimensional computing.
Proceedings of the 2018 IEEE EMBS International Conference on Biomedical & Health Informatics, 2018

2017
High-Dimensional Computing as a Nanoscalable Paradigm.
IEEE Trans. on Circuits and Systems, 2017

Low-Power Sparse Hyperdimensional Encoder for Language Recognition.
IEEE Design & Test, 2017

An 826 MOPS, 210 uW/MHz Unum ALU in 65 nm.
CoRR, 2017

Autoscaling Bloom Filter: Controlling Trade-off Between True and False Positives.
CoRR, 2017

Human-centric computing - The case for a Hyper-Dimensional approach.
Proceedings of the 7th IEEE International Workshop on Advances in Sensors and Interfaces, 2017

VoiceHD: Hyperdimensional Computing for Efficient Speech Recognition.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Exploring Hyperdimensional Associative Memory.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

SLoT: A supervised learning model to predict dynamic timing errors of functional units.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Efficient neural network acceleration on GPGPU using content addressable memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques From Circuits to Software.
Proceedings of the IEEE, 2016

Associative Memristive Memory for Approximate Computing in GPUs.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

CIRCA-GPUs: Increasing Instruction Reuse Through Inexact Computing in GP-GPUs.
IEEE Design & Test, 2016

A low-power hybrid magnetic cache architecture exploiting narrow-width values.
Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016

A Robust and Energy-Efficient Classifier Using Brain-Inspired Hyperdimensional Computing.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

ACAM: Approximate Computing Based on Adaptive Associative Memory with Online Learning.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Hyperdimensional biosignal processing: A case study for EMG-based hand gesture recognition.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016

WILD: A workload-based learning model to predict dynamic delay of functional units.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Grater: An approximation workflow for exploiting data-level parallelism in FPGA acceleration.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Resistive configurable associative memory for approximate computing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Resistive Bloom filters: From approximate membership to approximate computing with bounded errors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
From Variability-Tolerance to Approximate Computing in Parallel Computing Architectures.
PhD thesis, 2015

Aging-Aware Compilation for GP-GPUs.
TACO, 2015

Axilog: Abstractions for Approximate Hardware Design and Reuse.
IEEE Micro, 2015

NSF expedition on variability-aware software: Recent results and contributions.
it - Information Technology, 2015

Supervised learning based model for predicting variability-induced timing errors.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Axilog: language support for approximate hardware design.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Approximate associative memristive memory for energy-efficient GPUs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Task scheduling strategies to mitigate hardware variability in embedded shared memory clusters.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Application-Adaptive Guardbanding to Mitigate Static and Dynamic Variability.
IEEE Trans. Computers, 2014

Improving Resilience to Timing Errors by Exposing Variability Effects to Software in Tightly-Coupled Processor Clusters.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Energy-efficient mapping of biomedical applications on domain-specific accelerator under process variation.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Temporal memoization for energy-efficient timing error recovery in GPGPUs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Energy-Efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-Based Computing.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Spatial Memoization: Concurrent Instruction Reuse to Correct Timing Errors in SIMD Architectures.
IEEE Trans. on Circuits and Systems, 2013

Variation-tolerant OpenMP tasking on tightly-coupled processor clusters.
Proceedings of the Design, Automation and Test in Europe, 2013

Hierarchically focused guardbanding: an adaptive approach to mitigate PVT variations and aging.
Proceedings of the Design, Automation and Test in Europe, 2013

Aging-aware compiler-directed VLIW assignment for GPGPU architectures.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

A variability-aware OpenMP environment for efficient execution of accuracy-configurable computation on shared-FPU processor clusters.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

ARGO: Aging-aware GPGPU register file allocation.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

2012
Procedure hopping: a low overhead solution to mitigate variability in shared-L1 processor clusters.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Analysis of instruction-level vulnerability to dynamic voltage and temperature variations.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Low-energy GALS NoC with FIFO - Monitoring dynamic voltage scaling.
Microelectronics Journal, 2011

A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
A High Throughput Low Power FIFO Used for GALS NoC Buffers.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010


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