Houman Homayoun

Orcid: 0000-0001-8904-4699

According to our database1, Houman Homayoun authored at least 256 papers between 2006 and 2024.

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Bibliography

2024
Optimized and Automated Secure IC Design Flow: A Defense-in-Depth Approach.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024

FFCL: Forward-Forward Net with Cortical Loops, Training and Inference on Edge Without Backpropagation.
CoRR, 2024

Automated Hardware Logic Obfuscation Framework Using GPT.
CoRR, 2024

Generative AI-Based Effective Malware Detection for Embedded Computing Systems.
CoRR, 2024

Fuzzing BusyBox: Leveraging LLM and Crash Reuse for Embedded Bug Unearthing.
CoRR, 2024

Intelligent Malware Detection based on Hardware Performance Counters: A Comprehensive Survey.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

LLM-FIN: Large Language Models Fingerprinting Attack on Edge Devices.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Securing On-Chip Learning: Navigating Vulnerabilities and Potential Safeguards in Spiking Neural Network Architectures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

IRET: Incremental Resolution Enhancing Transformer.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

FFCL: Forward-Forward Net with Cortical Loops, Training and Inference on Edge Without Backpropogation.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

SpecScope: Automating Discovery of Exploitable Spectre Gadgets on Black-Box Microarchitectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Hardware Trojan Detection Using Machine Learning: A Tutorial.
ACM Trans. Embed. Comput. Syst., 2023

Adversarial Attacks Against Machine Learning-Based Resource Provisioning Systems.
IEEE Micro, 2023

HW-V2W-Map: Hardware Vulnerability to Weakness Mapping Framework for Root Cause Analysis with GPT-assisted Mitigation Suggestion.
CoRR, 2023

Large Language Models for Code Analysis: Do LLMs Really Do Their Job?
CoRR, 2023

SMOOT: Saliency Guided Mask Optimized Online Training.
CoRR, 2023

Side Channel-Assisted Inference Leakage from Machine Learning-based ECG Classification.
CoRR, 2023

Advanced Reinforcement Learning Solution for Clock Skew Engineering: Modified Q-Table Update Technique for Peak Current and IR Drop Minimization.
IEEE Access, 2023

HeteroScore: Evaluating and Mitigating Cloud Security Threats Brought by Heterogeneity.
Proceedings of the 30th Annual Network and Distributed System Security Symposium, 2023

Securing AI Hardware: Challenges in Detecting and Mitigating Hardware Trojans in ML Accelerators.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Leveraging Firmware Reverse Engineering for Stealthy Sensor Attacks via Binary Modification.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

Side Channel-Assisted Inference Attacks on Machine Learning-Based ECG Classification.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Privee: A Wearable for Real-Time Bladder Monitoring System.
Proceedings of the Adjunct Proceedings of the 2023 ACM International Joint Conference on Pervasive and Ubiquitous Computing & the 2023 ACM International Symposium on Wearable Computing, 2023

Federated Learning with Heterogeneous Models for On-device Malware Detection in IoT Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Don't Cross Me! Cross-layer System Security.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Special Session: Mitigating Side-Channel Attacks Through Circuit to Application Layer Approaches.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023

Short: Real-Time Bladder Monitoring by Bio-impedance Analysis to Aid Urinary Incontinence.
Proceedings of the IEEE/ACM Conference on Connected Health: Applications, 2023

Gotcha! I Know What You Are Doing on the FPGA Cloud: Fingerprinting Co-Located Cloud FPGA Accelerators via Measuring Communication Links.
Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security, 2023

Emotion and Stress Recognition Utilizing Galvanic Skin Response and Wearable Technology: A Real-time Approach for Mental Health Care.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2023

Introducing an Open-Source Python Toolkit for Machine Learning Research in Physiological Signal based Affective Computing.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2023

2022
Breaking the Design and Security Trade-off of Look-up-table-based Obfuscation.
ACM Trans. Design Autom. Electr. Syst., 2022

A Neural Network-Based Cognitive Obfuscation Toward Enhanced Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Imitating Functional Operations for Mitigating Side-Channel Leakage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Hardware Accelerator for Language-Guided Reinforcement Learning.
IEEE Des. Test, 2022

Automatic Detection of Respiratory Symptoms Using a Low-Power Multi-Input CNN Processor.
IEEE Des. Test, 2022

A Neural Network-based SAT-Resilient Obfuscation Towards Enhanced Logic Locking.
CoRR, 2022

Neuromorphic-Enabled Security for IoT.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

FANDEMIC: Firmware Attack Construction and Deployment on Power Management Integrated Circuit and Impacts on IoT Applications.
Proceedings of the 29th Annual Network and Distributed System Security Symposium, 2022

Repttack: Exploiting Cloud Schedulers to Guide Co-Location Attacks.
Proceedings of the 29th Annual Network and Distributed System Security Symposium, 2022

Adaptive-Gravity: A Defense Against Adversarial Samples.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Iron-Dome: Securing IoT Networked Systems at Runtime by Network and Device Characteristics to Confine Malware Epidemics.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Breakthrough to Adaptive and Cost-Aware Hardware-Assisted Zero-Day Malware Detection: A Reinforcement Learning-Based Approach.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

RAFeL - Robust and Data-Aware Federated Learning-inspired Malware Detection in Internet-of-Things (IoT) Networks.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

CAD-FSL: Code-Aware Data Generation based Few-Shot Learning for Efficient Malware Detection.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Deep Neural Network and Transfer Learning for Accurate Hardware-Based Zero-Day Malware Detection.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Survey of Machine Learning for Electronic Design Automation.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing Analysis.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

DNN Model Architecture Fingerprinting Attack on CPU-GPU Edge Devices.
Proceedings of the 7th IEEE European Symposium on Security and Privacy, 2022

Convolution Neural Network for Pain Intensity Assessment from Facial Expression.
Proceedings of the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2022

ATLAS: An Adaptive Transfer Learning Based Pain Assessment System: A Real Life Unsupervised Pain Assessment Solution.
Proceedings of the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2022

Stealthy Inference Attack on DNN via Cache-based Side-Channel Attacks.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

CR-Spectre: Defense-Aware ROP Injected Code-Reuse Based Dynamic Spectre.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

LOCK&ROLL: deep-learning power side-channel attack mitigation using emerging reconfigurable devices and logic locking.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Silicon validation of LUT-based logic-locked IP cores.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

A Low Cost EDA-based Stress Detection Using Machine Learning.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2022

Prevent Over-fitting and Redundancy in Physiological Signal Analyses for Stress Detection.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2022

Towards Generalized ML Model in Automated Physiological Arousal Computing: A Transfer Learning-Based Domain Generalization Approach.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2022

2021
Cyclic Sparsely Connected Architectures for Compact Deep Convolutional Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Adaptive Performance Modeling of Data-intensive Workloads for Resource Provisioning in Virtualized Environment.
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2021

Deep graph transformation for attributed, directed, and signed networks.
Knowl. Inf. Syst., 2021

Deep Graph Learning for Circuit Deobfuscation.
Frontiers Big Data, 2021

Enabling Micro AI for Securing Edge Devices at Hardware Level.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Guest Editorial Cross-Layer Designs, Methodologies, and Systems to Enable Micro AI for On-Device Intelligence.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Towards Accurate Run-Time Hardware-Assisted Stealthy Malware Detection: A Lightweight, yet Effective Time Series CNN-Based Approach.
Cryptogr., 2021

AVATAR: NN-Assisted Variation Aware Timing Analysis and Reporting for Hardware Trojan Detection.
IEEE Access, 2021

From Cryptography to Logic Locking: A Survey on the Architecture Evolution of Secure Scan Chains.
IEEE Access, 2021

Security Threats in Cloud Rooted from Machine Learning-Based Resource Provisioning Systems.
Proceedings of the Silicon Valley Cybersecurity Conference - Second Conference, 2021

Power Swapper: Approximate Functional Block Assisted Cryptosystem Security.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

Ontology-Driven Framework for Trend Analysis of Vulnerabilities and Impacts in IoT Hardware.
Proceedings of the 15th IEEE International Conference on Semantic Computing, 2021

Cloak & Co-locate: Adversarial Railroading of Resource Sharing-based Attacks on the Cloud.
Proceedings of the 2021 International Symposium on Secure and Private Execution Environment Design (SEED), 2021

Machine Learning-Assisted Website Fingerprinting Attacks with Side-Channel Information: A Comprehensive Analysis and Characterization.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Conditional Classification: A Solution for Computational Energy Reduction.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Diverse Knowledge Distillation (DKD): A Solution for Improving The Robustness of Ensemble Models Against Adversarial Attacks.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

ChaoLock: Yet Another SAT-hard Logic Locking using Chaos Computing.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

When Machine Learning Meets Hardware Cybersecurity: Delving into Accurate Zero-Day Malware Detection.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Adaptive-HMD: Accurate and Cost-Efficient Machine Learning-Driven Malware Detection using Microarchitectural Events.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

HosNa: A DPC++ Benchmark Suite for Heterogeneous Architectures.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Performance-aware Malware Epidemic Confinement in Large-Scale IoT Networks.
Proceedings of the ICC 2021, 2021

RANE: An Open-Source Formal De-obfuscation Attack for Reverse Engineering of Logic Encrypted Circuits.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Energy-Efficient and Adversarially Robust Machine Learning with Selective Dynamic Band Filtering.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

A Cognitive SAT to SAT-Hard Clause Translation-based Logic Obfuscation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

HMD-Hardener: Adversarially Robust and Efficient Hardware-Assisted Runtime Malware Detection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

StocHD: Stochastic Hyperdimensional System for Efficient and Robust Learning from Raw Data.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Securing Hardware via Dynamic Obfuscation Utilizing Reconfigurable Interconnect and Logic Blocks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Evaluation of Machine Learning-based Detection against Side-Channel Attacks on Autonomous Vehicle.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

Demography-aware COVID-19 Confinement with Game Theory.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
SAT-Hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain.
IEEE Trans. Very Large Scale Integr. Syst., 2020

ICNN: The Iterative Convolutional Neural Network.
ACM Trans. Embed. Comput. Syst., 2020

Cluster-Based Partitioning of Convolutional Neural Networks, A Solution for Computational Energy and Complexity Reduction.
CoRR, 2020

Learning Diverse Latent Representations for Improving the Resilience to Adversarial Attacks.
CoRR, 2020

Cognitive and Scalable Technique for Securing IoT Networks Against Malware Epidemics.
IEEE Access, 2020

DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Recent Advancements in Microarchitectural Security: Review of Machine Learning Countermeasures.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

R2AD: Randomization and Reconstructor-based Adversarial Defense on Deep Neural Network.
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

LASCA: Learning Assisted Side Channel Delay Analysis for Hardware Trojan Detection.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

CSCMAC - Cyclic Sparsely Connected Neural Network Manycore Accelerator.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

SATConda: SAT to SAT-Hard Clause Translator.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Entropy-Shield: Side-Channel Entropy Maximization for Timing-based Side-Channel Attacks.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Code-Bridged Classifier (CBC): A Low or Negative Overhead Defense for Making a CNN Classifier Robust Against Adversarial Attacks.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

SCARF: Detecting Side-Channel Attacks at Real-time using Low-level Hardware Features.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

HybriDG: Hybrid Dynamic Time Warping and Gaussian Distribution Model for Detecting Emerging Zero-Day Microarchitectural Side-Channel Attacks.
Proceedings of the 19th IEEE International Conference on Machine Learning and Applications, 2020

Phased-Guard: Multi-Phase Machine Learning Framework for Detection and Identification of Zero-Day Microarchitectural Side-Channel Attacks.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Hybrid-Shield: Accurate and Efficient Cross-Layer Countermeasure for Run-Time Detection and Mitigation of Cache-Based Side-Channel Attacks.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

InterLock: An Intercorrelated Logic and Routing Locking.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Comprehensive Evaluation of Machine Learning Countermeasures for Detecting Microarchitectural Side-Channel Attacks.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Energy-Efficient Hardware for Language Guided Reinforcement Learning.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

StealthMiner: Specialized Time Series Machine Learning for Run-Time Stealthy Malware Detection based on Microarchitectural Features.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Mitigating Cache-Based Side-Channel Attacks through Randomization: A Comprehensive System and Architecture Level Analysis.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Estimating the Circuit De-obfuscation Runtime based on Graph Deep Learning.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

NESTA: Hamming Weight Compression-Based Neural Proc. EngineAli Mirzaeian.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Big vs little core for energy-efficient Hadoop computing.
J. Parallel Distributed Comput., 2019

Application and Thermal-reliability-aware Reinforcement Learning Based Multi-core Power Management.
ACM J. Emerg. Technol. Comput. Syst., 2019

NESTA: Hamming Weight Compression-Based Neural Proc. Engine.
CoRR, 2019

Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design.
CoRR, 2019

Estimating the Circuit Deobfuscating Runtime based on Graph Deep Learning.
CoRR, 2019

TCD-NPE: A Re-configurable and Efficient Neural Processing Engine, Powered by Novel Temporal-Carry-deferring MACs.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

COMA: Communication and Obfuscation Management Architecture.
Proceedings of the 22nd International Symposium on Research in Attacks, 2019

Exploiting Energy-Accuracy Trade-off through Contextual Awareness in Multi-Stage Convolutional Neural Networks.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

ECoST: Energy-Efficient Co-Locating and Self-Tuning MapReduce Applications.
Proceedings of the 48th International Conference on Parallel Processing, 2019

A+ Tuning: Architecture+Application Auto-Tuning for In-Memory Data-Processing Frameworks.
Proceedings of the 25th IEEE International Conference on Parallel and Distributed Systems, 2019

Deep Multi-attributed Graph Translation with Node-Edge Co-Evolution.
Proceedings of the 2019 IEEE International Conference on Data Mining, 2019

DynGraph2Seq: Dynamic-Graph-to-Sequence Interpretable Learning for Health Stage Prediction in Online Health Forums.
Proceedings of the 2019 IEEE International Conference on Data Mining, 2019

Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality.
Proceedings of the International Conference on Computer-Aided Design, 2019

Mitigating the Performance and Quality of Parallelized Compressive Sensing Reconstruction Using Image Stitching.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

On Custom LUT-based Obfuscation.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Threats on Logic Locking: A Decade Later.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Lightweight Node-level Malware Detection and Network-level Malware Confinement in IoT Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

On the Complexity Reduction of Dense Layers from O(N2) to O(NlogN) with Cyclic Sparsely Connected Layers.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Adversarial Attack on Microarchitectural Events based Malware Detectors.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Parallel Multi-View Graph Matrix Completion for Large Input Matrix.
Proceedings of the IEEE 9th Annual Computing and Communication Workshop and Conference, 2019

SAT to SAT-Hard Clause Translator.
Proceedings of the 2019 International Conference on Compliers, 2019

Sequence-Crafter: Side-Channel Entropy Minimization to Thwart Timing-based Side-Channel Attacks.
Proceedings of the 2019 International Conference on Compliers, 2019

Resource-Efficient Wearable Computing for Real-Time Reconfigurable Machine Learning: A Cascading Binary Classification.
Proceedings of the 16th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2019

IR-ATA: IR annotated timing analysis, a flow for closing the loop between PDN design, IR analysis & timing closure.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

XPPE: cross-platform performance estimation of hardware accelerators using machine learning.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal Dependence.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Sparse Regression Driven Mixture Importance Sampling for Memory Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018

An Energy-Efficient Programmable Manycore Accelerator for Personalized Biomedical Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2018

System and Architecture Level Characterization of Big Data Applications on Big and Little Core Server Architectures.
ACM Trans. Model. Perform. Evaluation Comput. Syst., 2018

Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering.
ACM Trans. Design Autom. Electr. Syst., 2018

Optimal Allocation of Computation and Communication in an IoT Network.
ACM Trans. Design Autom. Electr. Syst., 2018

Hardware Accelerated Mappers for Hadoop MapReduce Streaming.
IEEE Trans. Multi Scale Comput. Syst., 2018

Hadoop Workloads Characterization for Performance and Energy Efficiency Optimizations on Microservers.
IEEE Trans. Multi Scale Comput. Syst., 2018

Low Overhead CS-Based Heterogeneous Framework for Big Data Acceleration.
ACM Trans. Embed. Comput. Syst., 2018

Energy-efficient acceleration of MapReduce applications using FPGAs.
J. Parallel Distributed Comput., 2018

Heterogeneous HMC+DDRx Memory Management for Performance-Temperature Tradeoffs.
ACM J. Emerg. Technol. Comput. Syst., 2018

Customized Machine Learning-Based Hardware-Assisted Malware Detection in Embedded Devices.
Proceedings of the 17th IEEE International Conference On Trust, 2018

Architectural considerations for FPGA acceleration of machine learning applications in MapReduce.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

A Scalable and Low Power DCNN for Multimodal Data Classification.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

A comprehensive memory analysis of data intensive workloads on server class architecture.
Proceedings of the International Symposium on Memory Systems, 2018

LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Efficient utilization of adversarial training towards robust machine learners and its analysis.
Proceedings of the International Conference on Computer-Aided Design, 2018

Design Space Exploration for Hardware Acceleration of Machine Learning Applications in MapReduce.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

ICNN: An iterative implementation of convolutional neural networks to enable energy and computational complexity aware dynamic approximation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classification.
Proceedings of the 55th Annual Design Automation Conference, 2018

Energy-aware and Machine Learning-based Resource Provisioning of In-Memory Analytics on Cloud.
Proceedings of the ACM Symposium on Cloud Computing, 2018

Comprehensive assessment of run-time hardware-supported malware detection using general and ensemble learning.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

Main-Memory Requirements of Big Data Applications on Commodity Server Platform.
Proceedings of the 18th IEEE/ACM International Symposium on Cluster, 2018

Advances and throwbacks in hardware-assisted security: special session.
Proceedings of the International Conference on Compilers, 2018

Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Compressive Sensing on Storage Data: An Effective Solution to Alleviate I/0 Bottleneck in Data- Intensive Workloads.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Editorial.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Power Delivery Network and Cell Placement Aware IR-Drop Mitigation Technique: Harvesting Unused Timing Slacks to Schedule Useful Skews.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Spatial and temporal scheduling of clock arrival times for IR hot-spot mitigation, reformulation of peak current reduction.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Co-locating and concurrent fine-tuning MapReduce applications on microservers for energy efficiency.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

Memory requirements of hadoop, spark, and MPI based big data applications on commodity server class architectures.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

MeNa: A memory navigator for modern hardware in a scale-out environment.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

Machine Learning-Based Approaches for Energy-Efficiency Prediction and Scheduling in Composite Cores Architectures.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Scheduling multithreaded applications onto heterogeneous composite cores architecture.
Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

Understanding the role of memory subsystem on performance and energy-efficiency of Hadoop applications.
Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Big vs little core for energy-efficient Hadoop computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

LESS: Big data sketching and Encryption on low power platform.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Analyzing Hardware Based Malware Detectors.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging.
Microelectron. Reliab., 2016

Comparative analysis of hybrid Magnetic Tunnel Junction and CMOS logic circuits.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Architecture Exploration for Energy-Efficient Embedded Vision Applications: From General Purpose Processor to Domain Specific Accelerator.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Preventing design reverse engineering with reconfigurable spin transfer torque LUT gates.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Characterizing Hadoop applications on microservers for performance and energy efficiency optimizations.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

Energy efficient on-chip power delivery with run-time voltage regulator clustering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Big biomedical image processing hardware acceleration: A case study for K-means and image filtering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Comparative analysis of robustness of spin transfer torque based look up tables under process variations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Dynamic single and Dual Rail spin transfer torque look up tables with enhanced robustness under CMOS and MTJ process variations.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Co-clustering of diseases, genes, and drugs for identification of their related gene modules.
Proceedings of the Eighth International Conference on Advanced Computational Intelligence, 2016

Load Balanced On-Chip Power Delivery for Average Current Demand.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Low-Power Manycore Accelerator for Personalized Biomedical Applications.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Hybrid STT-CMOS designs for reverse-engineering prevention.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Big data analytics on heterogeneous accelerator architectures.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Heterogeneous chip multiprocessor architectures for big data applications.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Using a Flexible Fault-Tolerant Cache to Improve Reliability for Ultra Low Voltage Operation.
ACM Trans. Embed. Comput. Syst., 2015

Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Power and performance characterization, analysis and tuning for energy-efficient edge detection on atom and ARM based platforms.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Big data on low power cores: Are low power embedded processors a good fit for the big data workloads?
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Wide I/O or LPDDR? Exploration and analysis of performance, power and temperature trade-offs of emerging DRAM technologies in embedded MPSoCs.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Revisiting Dynamic Thermal Management Exploiting Inverse Thermal Dependence.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Adaptive Bandwidth Management for Performance-Temperature Trade-offs in Heterogeneous HMC+DDRx Memory.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Accelerating Big Data Analytics Using FPGAs.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Just-in-time component-wise power and thermal modeling.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

Accelerating Machine Learning Kernel in Hadoop Using FPGAs.
Proceedings of the 15th IEEE/ACM International Symposium on Cluster, 2015

Energy-efficient acceleration of big data analytics applications using FPGAs.
Proceedings of the 2015 IEEE International Conference on Big Data (IEEE BigData 2015), Santa Clara, CA, USA, October 29, 2015

System and architecture level characterization of big data applications on big and little core server architectures.
Proceedings of the 2015 IEEE International Conference on Big Data (IEEE BigData 2015), Santa Clara, CA, USA, October 29, 2015

2014
Multicopy Cache: A Highly Energy-Efficient Cache Architecture.
ACM Trans. Embed. Comput. Syst., 2014

Resistive Computation: A Critique.
IEEE Comput. Archit. Lett., 2014

Energy-efficient mapping of biomedical applications on domain-specific accelerator under process variation.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Modeling and analysis of Phase Change Materials for efficient thermal management.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

NVP: Non-uniform voltage and pulse width settings for power efficient hybrid STT-RAM.
Proceedings of the International Green Computing Conference, 2014

A parallel and reconfigurable architecture for efficient OMP compressive sensing reconstruction.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Reconfigurable STT-NV LUT-based functional units to improve performance in general-purpose processors.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Exploiting STT-NV technology for reconfigurable, high performance, low power, and low temperature functional unit design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Enabling Dynamic Heterogeneity Through Core-on-Core Stacking.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Temperature aware thread migration in 3D architecture with stacked DRAM.
Proceedings of the International Symposium on Quality Electronic Design, 2013

A 64-core platform for biomedical signal processing.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Low-current probabilistic writes for power-efficient STT-RAM caches.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

VAWOM: temperature and process variation aware wearout management in 3D multicore architecture.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Heterogeneous memory management for 3D-DRAM and external DRAM with QoS.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2012

History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Hot peripheral thermal management to mitigate cache temperature variation.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Managing distributed UPS energy for effective power capping in data centers.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Dynamically heterogeneous cores through 3D resource pooling.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011
Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation.
IEEE Trans. Very Large Scale Integr. Syst., 2011

MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management.
IEEE Trans. Very Large Scale Integr. Syst., 2011

On leakage power optimization in clock tree networks for ASICs and general-purpose processors.
Sustain. Comput. Informatics Syst., 2011

Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operation.
Proceedings of the 14th International Conference on Compilers, 2011

2010
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010

Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.
Proceedings of the 7th Conference on Computing Frontiers, 2010

E < MC2: less energy through multi-copy cache.
Proceedings of the 2010 International Conference on Compilers, 2010

2009
Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling.
Proceedings of the Design, Automation and Test in Europe, 2009

A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).
Proceedings of the 2009 International Conference on Compilers, 2009

2008
A centralized cache miss driven technique to improve processor power dissipation.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors.
Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008

Adaptive techniques for leakage power management in L2 cache peripheral circuits.
Proceedings of the 26th International Conference on Computer Design, 2008

ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits.
Proceedings of the 26th International Conference on Computer Design, 2008

Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency.
Proceedings of the 45th Design Automation Conference, 2008

Multiple sleep mode leakage control for cache peripheral circuits in embedded processors.
Proceedings of the 2008 International Conference on Compilers, 2008

2007
Reducing leakage power in peripheral circuits of L2 caches.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
Reducing Execution Unit Leakage Power in Embedded Processors.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Reducing the Instruction Queue Leakage Power in Superscalar Processors.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006


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