Houman Homayoun

According to our database1, Houman Homayoun authored at least 127 papers between 2006 and 2019.

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Bibliography

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. VLSI Syst., 2019

SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Big vs little core for energy-efficient Hadoop computing.
J. Parallel Distrib. Comput., 2019

Exploiting Energy-Accuracy Trade-off through Contextual Awareness in Multi-Stage Convolutional Neural Networks.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

ECoST: Energy-Efficient Co-Locating and Self-Tuning MapReduce Applications.
Proceedings of the 48th International Conference on Parallel Processing, 2019

Mitigating the Performance and Quality of Parallelized Compressive Sensing Reconstruction Using Image Stitching.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

On Custom LUT-based Obfuscation.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Threats on Logic Locking: A Decade Later.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Lightweight Node-level Malware Detection and Network-level Malware Confinement in IoT Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

On the Complexity Reduction of Dense Layers from O(N2) to O(NlogN) with Cyclic Sparsely Connected Layers.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Adversarial Attack on Microarchitectural Events based Malware Detectors.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Resource-Efficient Wearable Computing for Real-Time Reconfigurable Machine Learning: A Cascading Binary Classification.
Proceedings of the 16th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2019

IR-ATA: IR annotated timing analysis, a flow for closing the loop between PDN design, IR analysis & timing closure.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

XPPE: cross-platform performance estimation of hardware accelerators using machine learning.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling.
IEEE Trans. VLSI Syst., 2018

Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal Dependence.
IEEE Trans. VLSI Syst., 2018

Sparse Regression Driven Mixture Importance Sampling for Memory Design.
IEEE Trans. VLSI Syst., 2018

An Energy-Efficient Programmable Manycore Accelerator for Personalized Biomedical Applications.
IEEE Trans. VLSI Syst., 2018

System and Architecture Level Characterization of Big Data Applications on Big and Little Core Server Architectures.
TOMPECS, 2018

Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering.
ACM Trans. Design Autom. Electr. Syst., 2018

Optimal Allocation of Computation and Communication in an IoT Network.
ACM Trans. Design Autom. Electr. Syst., 2018

Hardware Accelerated Mappers for Hadoop MapReduce Streaming.
IEEE Trans. Multi-Scale Computing Systems, 2018

Hadoop Workloads Characterization for Performance and Energy Efficiency Optimizations on Microservers.
IEEE Trans. Multi-Scale Computing Systems, 2018

Low Overhead CS-Based Heterogeneous Framework for Big Data Acceleration.
ACM Trans. Embedded Comput. Syst., 2018

Energy-efficient acceleration of MapReduce applications using FPGAs.
J. Parallel Distrib. Comput., 2018

Heterogeneous HMC+DDRx Memory Management for Performance-Temperature Tradeoffs.
JETC, 2018

Customized Machine Learning-Based Hardware-Assisted Malware Detection in Embedded Devices.
Proceedings of the 17th IEEE International Conference On Trust, 2018

Architectural considerations for FPGA acceleration of machine learning applications in MapReduce.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

A Scalable and Low Power DCNN for Multimodal Data Classification.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

A comprehensive memory analysis of data intensive workloads on server class architecture.
Proceedings of the International Symposium on Memory Systems, 2018

LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Efficient utilization of adversarial training towards robust machine learners and its analysis.
Proceedings of the International Conference on Computer-Aided Design, 2018

Design Space Exploration for Hardware Acceleration of Machine Learning Applications in MapReduce.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

ICNN: An iterative implementation of convolutional neural networks to enable energy and computational complexity aware dynamic approximation.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classification.
Proceedings of the 55th Annual Design Automation Conference, 2018

Energy-aware and Machine Learning-based Resource Provisioning of In-Memory Analytics on Cloud.
Proceedings of the ACM Symposium on Cloud Computing, 2018

Comprehensive assessment of run-time hardware-supported malware detection using general and ensemble learning.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

Main-Memory Requirements of Big Data Applications on Commodity Server Platform.
Proceedings of the 18th IEEE/ACM International Symposium on Cluster, 2018

Advances and throwbacks in hardware-assisted security: special session.
Proceedings of the International Conference on Compilers, 2018

Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Compressive Sensing on Storage Data: An Effective Solution to Alleviate I/0 Bottleneck in Data- Intensive Workloads.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery.
IEEE Trans. VLSI Syst., 2017

Editorial.
IEEE Trans. VLSI Syst., 2017

A Power Delivery Network and Cell Placement Aware IR-Drop Mitigation Technique: Harvesting Unused Timing Slacks to Schedule Useful Skews.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Spatial and temporal scheduling of clock arrival times for IR hot-spot mitigation, reformulation of peak current reduction.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Co-locating and concurrent fine-tuning MapReduce applications on microservers for energy efficiency.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

Memory requirements of hadoop, spark, and MPI based big data applications on commodity server class architectures.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

MeNa: A memory navigator for modern hardware in a scale-out environment.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

Machine Learning-Based Approaches for Energy-Efficiency Prediction and Scheduling in Composite Cores Architectures.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Scheduling multithreaded applications onto heterogeneous composite cores architecture.
Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

Understanding the role of memory subsystem on performance and energy-efficiency of Hadoop applications.
Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Big vs little core for energy-efficient Hadoop computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

LESS: Big data sketching and Encryption on low power platform.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Analyzing Hardware Based Malware Detectors.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging.
Microelectronics Reliability, 2016

Comparative analysis of hybrid Magnetic Tunnel Junction and CMOS logic circuits.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Architecture Exploration for Energy-Efficient Embedded Vision Applications: From General Purpose Processor to Domain Specific Accelerator.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Preventing design reverse engineering with reconfigurable spin transfer torque LUT gates.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Characterizing Hadoop applications on microservers for performance and energy efficiency optimizations.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

Energy efficient on-chip power delivery with run-time voltage regulator clustering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Big biomedical image processing hardware acceleration: A case study for K-means and image filtering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Comparative analysis of robustness of spin transfer torque based look up tables under process variations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Dynamic single and Dual Rail spin transfer torque look up tables with enhanced robustness under CMOS and MTJ process variations.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Co-clustering of diseases, genes, and drugs for identification of their related gene modules.
Proceedings of the Eighth International Conference on Advanced Computational Intelligence, 2016

Load Balanced On-Chip Power Delivery for Average Current Demand.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Low-Power Manycore Accelerator for Personalized Biomedical Applications.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Hybrid STT-CMOS designs for reverse-engineering prevention.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Big data analytics on heterogeneous accelerator architectures.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Heterogeneous chip multiprocessor architectures for big data applications.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Using a Flexible Fault-Tolerant Cache to Improve Reliability for Ultra Low Voltage Operation.
ACM Trans. Embedded Comput. Syst., 2015

Realizing complexity-effective on-chip power delivery for many-core platforms by exploiting optimized mapping.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Power and performance characterization, analysis and tuning for energy-efficient edge detection on atom and ARM based platforms.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Big data on low power cores: Are low power embedded processors a good fit for the big data workloads?
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Wide I/O or LPDDR? Exploration and analysis of performance, power and temperature trade-offs of emerging DRAM technologies in embedded MPSoCs.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Revisiting Dynamic Thermal Management Exploiting Inverse Thermal Dependence.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Adaptive Bandwidth Management for Performance-Temperature Trade-offs in Heterogeneous HMC+DDRx Memory.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Accelerating Big Data Analytics Using FPGAs.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Just-in-time component-wise power and thermal modeling.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

Accelerating Machine Learning Kernel in Hadoop Using FPGAs.
Proceedings of the 15th IEEE/ACM International Symposium on Cluster, 2015

Energy-efficient acceleration of big data analytics applications using FPGAs.
Proceedings of the 2015 IEEE International Conference on Big Data, 2015

System and architecture level characterization of big data applications on big and little core server architectures.
Proceedings of the 2015 IEEE International Conference on Big Data, 2015

2014
Multicopy Cache: A Highly Energy-Efficient Cache Architecture.
ACM Trans. Embedded Comput. Syst., 2014

Resistive Computation: A Critique.
Computer Architecture Letters, 2014

Energy-efficient mapping of biomedical applications on domain-specific accelerator under process variation.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Modeling and analysis of Phase Change Materials for efficient thermal management.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

NVP: Non-uniform voltage and pulse width settings for power efficient hybrid STT-RAM.
Proceedings of the International Green Computing Conference, 2014

A parallel and reconfigurable architecture for efficient OMP compressive sensing reconstruction.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Reconfigurable STT-NV LUT-based functional units to improve performance in general-purpose processors.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Exploiting STT-NV technology for reconfigurable, high performance, low power, and low temperature functional unit design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Enabling Dynamic Heterogeneity Through Core-on-Core Stacking.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Temperature aware thread migration in 3D architecture with stacked DRAM.
Proceedings of the International Symposium on Quality Electronic Design, 2013

A 64-core platform for biomedical signal processing.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Low-current probabilistic writes for power-efficient STT-RAM caches.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

VAWOM: temperature and process variation aware wearout management in 3D multicore architecture.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Heterogeneous memory management for 3D-DRAM and external DRAM with QoS.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling.
IEEE Trans. VLSI Syst., 2012

History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Hot peripheral thermal management to mitigate cache temperature variation.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Managing distributed UPS energy for effective power capping in data centers.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Dynamically heterogeneous cores through 3D resource pooling.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011
Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation.
IEEE Trans. VLSI Syst., 2011

MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits.
IEEE Trans. VLSI Syst., 2011

Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management.
IEEE Trans. VLSI Syst., 2011

On leakage power optimization in clock tree networks for ASICs and general-purpose processors.
SUSCOM, 2011

Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operation.
Proceedings of the 14th International Conference on Compilers, 2011

2010
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010

Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.
Proceedings of the 7th Conference on Computing Frontiers, 2010

E < MC2: less energy through multi-copy cache.
Proceedings of the 2010 International Conference on Compilers, 2010

2009
Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling.
Proceedings of the Design, Automation and Test in Europe, 2009

A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).
Proceedings of the 2009 International Conference on Compilers, 2009

2008
A centralized cache miss driven technique to improve processor power dissipation.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors.
Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008

Adaptive techniques for leakage power management in L2 cache peripheral circuits.
Proceedings of the 26th International Conference on Computer Design, 2008

ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits.
Proceedings of the 26th International Conference on Computer Design, 2008

Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency.
Proceedings of the 45th Design Automation Conference, 2008

Multiple sleep mode leakage control for cache peripheral circuits in embedded processors.
Proceedings of the 2008 International Conference on Compilers, 2008

2007
Reducing leakage power in peripheral circuits of L2 caches.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
Reducing Execution Unit Leakage Power in Embedded Processors.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Reducing the Instruction Queue Leakage Power in Superscalar Processors.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006


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