Anant Vishnoi

According to our database, Anant Vishnoi authored at least 4 papers between 2009 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

Compressing Cache State for Postsilicon Processor Debug.

Preeti Ranjan Panda, M. Balakrishnan, Anant Vishnoi

IEEE Trans. Computers, 2011

2010

Enhancing post-silicon processor debug with Incremental Cache state Dumping.

Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

2009

Cache aware compression for processor debug support.

Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan

Proceedings of the Design, Automation and Test in Europe, 2009

Online cache state dumping for processor debug.

Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan

Proceedings of the 46th Design Automation Conference, 2009