Preeti Ranjan Panda

According to our database1, Preeti Ranjan Panda authored at least 89 papers between 1991 and 2018.

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Bibliography

2018
Reusing Trace Buffers as Victim Caches.
IEEE Trans. VLSI Syst., 2018

Exploration of Loop Unroll Factors in High Level Synthesis.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2017
Managing Trace Summaries to Minimize Stalls During Postsilicon Validation.
IEEE Trans. VLSI Syst., 2017

Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network.
TACO, 2017

Reusing trace buffers to enhance cache performance.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Area-Aware Cache Update Trackers for Postsilicon Validation.
IEEE Trans. VLSI Syst., 2016

Partitioning and Data Mapping in Reconfigurable Cache and Scratchpad Memory-Based Architectures.
ACM Trans. Design Autom. Electr. Syst., 2016

Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures.
ACM Trans. Embedded Comput. Syst., 2016

Data Flow Transformation for Energy-Efficient Implementation of Givens Rotation-Based QRD.
ACM Trans. Embedded Comput. Syst., 2016

A Generic Implementation of Barriers Using Optical Interconnects.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Machine Learned Machines: Adaptive co-optimization of caches, cores, and On-chip Network.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Extending trace history through tapered summaries in post-silicon validation.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Array Interleaving - An Energy-Efficient Data Layout Transformation.
ACM Trans. Design Autom. Electr. Syst., 2015

Fundamental Results for a Generic Implementation of Barriers using Optical Interconnects.
CoRR, 2015

Power Optimization Techniques for DDR3 SDRAM.
Proceedings of the 28th International Conference on VLSI Design, 2015

Energy efficient FFT implementation through stage skipping and merging.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

2014
Shared-port register file architecture for low-energy VLIW processors.
TACO, 2014

High level energy modeling of controller logic in data caches.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Energy efficient data flow transformation for Givens Rotation based QR Decomposition.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Energy optimization in Android applications through wakelock placement.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Array scalarization in high level synthesis.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Power Supply Efficiency Aware Server Allocation in Data Centers.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Data memory optimization in LTE downlink.
Proceedings of the IEEE International Conference on Acoustics, 2013

Space sensitive cache dumping for post-silicon validation.
Proceedings of the Design, Automation and Test in Europe, 2013

Message from the program co-chairs.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

SPM-Sieve: A framework for assisting data partitioning in scratch pad memory based systems.
Proceedings of the International Conference on Compilers, 2013

2012
Exploiting UML based validation for compliance checking of TLM 2 based models.
Design Autom. for Emb. Sys., 2012

Efficient on-line algorithm for maintaining k-cover of sparse bit-strings.
Proceedings of the IARCS Annual Conference on Foundations of Software Technology and Theoretical Computer Science, 2012

Integrating software caches with scratch pad memory.
Proceedings of the 15th International Conference on Compilers, 2012

2011
Compressing Cache State for Postsilicon Processor Debug.
IEEE Trans. Computers, 2011

A UML based framework for efficient validation of TLM 2 models.
Proceedings of the 2011 Forum on Specification & Design Languages, 2011

A SysML Profile for Development and Early Validation of TLM 2.0 Models.
Proceedings of the Modelling Foundations and Applications - 7th European Conference, 2011

Exploiting temporal decoupling to accelerate trace-driven NoC emulation.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010
Guest Editorial: Special Issue on VLSI Design and Embedded Systems.
International Journal of Parallel Programming, 2010

Front-End Design Flows for Systems on Chip: An Embedded Tutorial.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Enhancing post-silicon processor debug with Incremental Cache state Dumping.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Rank based dynamic voltage and frequency scaling fortiled graphics processors.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009
A Special Issue on the "22nd IEEE International Conference on VLSI Design" New Delhi, India, 5-9 January 2009.
J. Low Power Electronics, 2009

Adaptive Partitioning of Vertex Shader for Low Power High Performance Geometry Engine.
Proceedings of the Advances in Visual Computing, 5th International Symposium, 2009

Cache aware compression for processor debug support.
Proceedings of the Design, Automation and Test in Europe, 2009

A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors.
Proceedings of the Design, Automation and Test in Europe, 2009

Online cache state dumping for processor debug.
Proceedings of the 46th Design Automation Conference, 2009

2008
Guest Editor Introduction: Special Issue on Multiprocessor-based Embedded Systems.
International Journal of Parallel Programming, 2008

Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

REWIRED - Register Write Inhibition by Resource Dedication.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.
International Journal of Parallel Programming, 2007

Customization of Register File Banking Architecture for Low Power.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Power Reduction in VLIW Processor with Compiler Driven Bypass Network.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

The impact of loop unrolling on controller delay in high level synthesis.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Rapid estimation of control delay from high-level specifications.
Proceedings of the 43rd Design Automation Conference, 2006

Abridged addressing: a low power memory addressing strategy.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Extracting Exact Finite State Machines from Behavioral SystemC Descriptions.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.
Proceedings of the 2005 Design, 2005

2003
Memory allocation and mapping in high-level synthesis - an integrated approach.
IEEE Trans. VLSI Syst., 2003

Specification and Design of Multi-Million Gate SOCs.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2002
An energy-conscious algorithm for memory port allocation.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Memory Architectures for Embedded Systems-On-Chip.
Proceedings of the High Performance Computing, 2002

An integrated algorithm for memory allocation and assignment in high-level synthesis.
Proceedings of the 39th Design Automation Conference, 2002

2001
Data and memory optimization techniques for embedded systems.
ACM Trans. Design Autom. Electr. Syst., 2001

Data Memory Organization and Optimizations in Application-Specific Systems.
IEEE Design & Test of Computers, 2001

Embedded Memories in System Design: Technology, Application, Design and Tools.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

New Design Paradigms: What Needs to be Standardized?.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Cache-efficient memory layout of aggregate data structures.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

SystemC: A Modeling Platform Supporting Multiple Design Abstractions.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

2000
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems.
ACM Trans. Design Autom. Electr. Syst., 2000

1999
Low-power memory mapping through reducing address bus activity.
IEEE Trans. VLSI Syst., 1999

Local memory exploration and optimization in embedded systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Augmenting Loop Tiling with Data Alignment for Improved Cache Performance.
IEEE Trans. Computers, 1999

Memory bank customization and assignment in behavioral synthesis.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998
Incorporating DRAM access modes into high-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Data Cache Sizing for Embedded Processor Applications.
Proceedings of the 1998 Design, 1998

1997
Memory data organization for improved cache performance in embedded processor applications.
ACM Trans. Design Autom. Electr. Syst., 1997

Behavioral Array Mapping into Multiport Memories Targeting Low Power.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Architectural Exploration and Optimization of Local Memory in Embedded Systems.
Proceedings of the 10th International Symposium on System Synthesis, 1997

Improving cache Performance Through Tiling and Data Alignment.
Proceedings of the Solving Irregularly Structured Problems in Parallel, 1997

A Data Alignment Technique for Improving Cache Performance.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Exploiting off-chip memory access modes in high-level synthesis.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Efficient utilization of scratch-pad memory in embedded processor applications.
Proceedings of the European Design and Test Conference, 1997

1996
Memory Organization for Improved Data Cache Performance in Embedded Processors.
Proceedings of the 9th International Symposium on System Synthesis, 1996

Low-power mapping of behavioral arrays to multiple memories.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Reducing Address Bus Transitions for Low Power Memory Mapping.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
1995 high level synthesis design repository.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

1993
Estimating the Complexity of Synthesized Designs from FSM Specifications.
IEEE Design & Test of Computers, 1993

1992
Estimating the Complexity of Synthesized Designs from FSM Specifications.
Proceedings of the Fifth International Conference on VLSI Design, 1992

1991
A Flexible Scheme for State Assignment Based on Characteristics of the FSM.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991


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