Andres Ayes

Orcid: 0000-0001-8829-0329

According to our database1, Andres Ayes authored at least 4 papers between 2023 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2025
Network-on-Interposer Co-Design for Heterogeneous Chiplet-Based Integrated Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024
Quasi-Adiabatic Clock Networks in 3-D Voltage Stacked Systems.
IEEE Trans. Very Large Scale Integr. Syst., December, 2024

2023
Linear Clock Tree Topology for Dynamic Source Synchronous and Fully Synchronous 3-D Interfaces.
Integr., November, 2023

Dual Sawtooth-Based Delay Locked Loops for Heterogeneous 3-D Clock Networks.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023


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