Andres Ayes

According to our database, Andres Ayes authored at least 5 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Active Interposers for High Bandwidth Memory.

Andres Ayes, Eby G. Friedman

Proceedings of the 27th International Symposium on Quality Electronic Design, 2026

2025

Network-on-Interposer Co-Design for Heterogeneous Chiplet-Based Integrated Systems.

Andres Ayes, Eby G. Friedman, Marilyn Wolf

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024

Quasi-Adiabatic Clock Networks in 3-D Voltage Stacked Systems.

Andres Ayes, Eby G. Friedman

IEEE Trans. Very Large Scale Integr. Syst., December, 2024

2023

Linear Clock Tree Topology for Dynamic Source Synchronous and Fully Synchronous 3-D Interfaces.

Andres Ayes, Eby G. Friedman

Integr., November, 2023

Dual Sawtooth-Based Delay Locked Loops for Heterogeneous 3-D Clock Networks.

Andres Ayes, Eby G. Friedman

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023