Eby G. Friedman

According to our database1, Eby G. Friedman authored at least 260 papers between 1991 and 2020.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2000, "For contributions to high performance circuit design and VLSI-based synchronous systems.".

Timeline

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On csauthors.net:

Bibliography

2020
Distributed Pass Gates in Power Delivery Systems With Digital Low-Dropout Regulators.
IEEE Trans. VLSI Syst., 2020

2019
Stability of On-Chip Power Delivery Systems With Multiple Low-Dropout Regulators.
IEEE Trans. VLSI Syst., 2019

Effective Resistance of Two-Dimensional Truncated Infinite Mesh Structures.
IEEE Trans. on Circuits and Systems, 2019

PMTJ Temperature Sensor Utilizing VCMA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Energy-Efficient Write Scheme for Nonvolatile Resistive Crossbar Arrays With Selectors.
IEEE Trans. VLSI Syst., 2018

Memristor-Based Circuit Design for Multilayer Neural Networks.
IEEE Trans. on Circuits and Systems, 2018

Exploratory design of on-chip power delivery for 14, 10, and 7 nm and beyond FinFET ICs.
Integr., 2018

Heterogeneous 3-D ICs as a platform for hybrid energy harvesting in IoT systems.
Future Gener. Comput. Syst., 2018

On the write energy of non-volatile resistive crossbar arrays with selectors.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Behavioral Verilog-A Model of Superconductor-Ferromagnetic Transistor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Hybrid Write Bias Scheme for Non-Volatile Resistive Crossbar Arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Versatile Framework for Power Delivery Exploration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

MTJ Magnetization Switching Mechanisms for IoT Applications.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017
Modeling Size Limitations of Resistive Crossbar Array With Cell Selectors.
IEEE Trans. VLSI Syst., 2017

Memristive Model for Synaptic Circuits.
IEEE Trans. on Circuits and Systems, 2017

Hexagonal TSV Bundle Topology for 3-D ICs.
IEEE Trans. on Circuits and Systems, 2017

Interconnect Delay Model for Wide Supply Voltage Range Repeater Insertion in Sub-22 nm FinFET Technologies.
J. Low Power Electronics, 2017

Hybrid energy harvesting in 3-D IC IoT devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Test point insertion for RSFQ circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low-Power Microprocessors.
IEEE Trans. VLSI Syst., 2016

Noise Coupling Models in Heterogeneous 3-D ICs.
IEEE Trans. VLSI Syst., 2016

Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits.
IEEE Trans. VLSI Syst., 2016

Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing.
IEEE Trans. VLSI Syst., 2016

Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS.
IEEE Trans. VLSI Syst., 2016

Heterogeneous 3-D circuits: Integrating free-space optics with CMOS.
Microelectron. J., 2016

Adaptive power gating of 32-bit Kogge Stone adder.
Integr., 2016

Layer ordering to minimize TSVs in heterogeneous 3-D ICs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Power noise in 14, 10, and 7 nm FinFET CMOS technologies.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Design models of resistive crossbar arrays with selector devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits.
IEEE Trans. VLSI Syst., 2015

Multistate Register Based on Resistive RAM.
IEEE Trans. VLSI Syst., 2015

VTEAM: A General Model for Voltage-Controlled Memristors.
IEEE Trans. on Circuits and Systems, 2015

Energy-Efficient Nonvolatile Flip-Flop With Subnanosecond Data Backup Time for Fine-Grain Power Gating.
IEEE Trans. on Circuits and Systems, 2015

Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing.
IEEE Micro, 2015

Scaling trends of power noise in 3-D ICs.
Integr., 2015

Energy efficient adaptive clustering of on-chip power delivery systems.
Integr., 2015

Inductive coupling effects in large TSV arrays.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

3-D floorplanning algorithm to minimize thermal interactions.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Architecting a MOS current mode logic (MCML) processor for fast, low noise and energy-efficient computing in the near-threshold regime.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014
Digitally Controlled Pulse Width Modulator for On-Chip Power Management.
IEEE Trans. VLSI Syst., 2014

Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies.
IEEE Trans. VLSI Syst., 2014

MAGIC - Memristor-Aided Logic.
IEEE Trans. on Circuits and Systems, 2014

2T-1R STT-MRAM memory cells for enhanced on/off current ratio.
Microelectron. J., 2014

Logic operations in memory using a memristive Akers array.
Microelectron. J., 2014

Memristor-Based Multithreading.
Computer Architecture Letters, 2014

Power network-on-chip for scalable power delivery.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014

Dynamic power management with power network-on-chip.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Sub-crosspoint RRAM decoding for improved area efficiency.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Thermal conduction path analysis in 3-D ICs.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Computationally efficient clustering of power supplies in heterogeneous real time systems.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Field driven STT-MRAM cell for reduced switching latency and energy.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Active Filter-Based Hybrid On-Chip DC-DC Converter for Point-of-Load Voltage Regulation.
IEEE Trans. VLSI Syst., 2013

Power Network Optimization Based on Link Breaking Methodology.
IEEE Trans. VLSI Syst., 2013

TEAM: ThrEshold Adaptive Memristor Model.
IEEE Trans. on Circuits and Systems, 2013

Data bus swizzling in TSV-based three-dimensional integrated circuits.
Microelectron. J., 2013

Power Noise in TSV-Based 3-D Integrated Circuits.
J. Solid-State Circuits, 2013

Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks.
Integr., 2013

Digitally controlled wide range pulse width modulator for on-chip power supplies.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Current profile of a microcontroller to determine electromagnetic emissions.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

AC-DIMM: associative computing with STT-MRAM.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012
Multi-aggressor capacitive and inductive coupling noise modeling and mitigation.
Microelectron. J., 2012

Utilizing interdependent timing constraints to enhance robustness in synchronous circuits.
Microelectron. J., 2012

Efficient algorithms for fast IR drop analysis exploiting locality.
Integr., 2012

Distributed On-Chip Power Delivery.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Arithmetic encoding for memristive multi-bit storage.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

STT-MRAM memory cells with enhanced on/off ratio.
Proceedings of the IEEE 25th International SOC Conference, 2012

An area efficient on-chip hybrid voltage regulator.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Energy metrics for power efficient crosslink and mesh topologies.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Link breaking methodology: mitigating noise within power networks.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Distributed power delivery for energy efficient and low power systems.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
Physical Analysis of NoC Topologies for 3-D Integrated Systems.
Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

Linear and Switch-Mode Conversion in 3-D Circuits.
IEEE Trans. VLSI Syst., 2011

A Distributed Filter Within a Switching Converter for Application to 3-D Integrated Circuits.
IEEE Trans. VLSI Syst., 2011

Clock Distribution Networks in 3-D Integrated Systems.
IEEE Trans. VLSI Syst., 2011

Shielding Methodologies in the Presence of Power/Ground Noise.
IEEE Trans. VLSI Syst., 2011

Multi-Layer Interdigitated Power Distribution Networks.
IEEE Trans. VLSI Syst., 2011

Effective Resistance of a Two Layer Mesh.
IEEE Trans. on Circuits and Systems, 2011

Thermal analysis of oxide-confined VCSEL arrays.
Microelectron. J., 2011

Distributed power network co-design with on-chip power supplies and decoupling capacitors.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

Clock distribution models of 3-D integrated systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Memristor-based IMPLY logic design procedure.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Fast algorithms for IR voltage drop analysis exploiting locality.
Proceedings of the 48th Design Automation Conference, 2011

2010
Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696].
IEEE Trans. VLSI Syst., 2010

Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect.
IEEE Trans. VLSI Syst., 2010

Resource Based Optimization for Simultaneous Shield and Repeater Insertion.
IEEE Trans. VLSI Syst., 2010

Simultaneous co-design of distributed on-chip power supplies and decoupling capacitors.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Fast algorithms for power grid analysis based on effective resistance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An area efficient fully monolithic hybrid voltage regulator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Compact substrate models for efficient noise coupling and signal isolation analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Methodology for multi-layer interdigitated power and ground network design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Globally integrated power and clock distribution network.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An intra-chip free-space optical interconnect.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Efficiency optimization of integrated DC-DC buck converters.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Methodology to achieve higher tolerance to delay variations in synchronous circuits.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

On-chip point-of-load voltage regulator for distributed power supplies.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Line width optimization for interdigitated power/ground networks.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Timing-driven variation-aware nonuniform clock mesh synthesis.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits.
IEEE Trans. VLSI Syst., 2009

Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling.
IEEE Trans. VLSI Syst., 2009

Quasi-Resonant Interconnects: A Low Power, Low Latency Design Methodology.
IEEE Trans. VLSI Syst., 2009

Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance.
IEEE Trans. on Circuits and Systems, 2009

Inductance Model of Interdigitated Power and Ground Distribution Networks.
IEEE Trans. on Circuits and Systems, 2009

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits.
Proceedings of the IEEE, 2009

Transient Response of a Distributed RLC Interconnect Based on Direct Pole Extraction.
Journal of Circuits, Systems, and Computers, 2009

On-chip DC-DC converters for three-dimensional ICs.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Minimizing Noise Via Shield and Repeater Insertion.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Power efficient tree-based crosslinks for skew reduction.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Contact merging algorithm for efficient substrate noise analysis in large scale circuits.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Simultaneous shield and repeater insertion.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Design challenges in high performance three-dimensional circuits.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008
Effective Radii of On-Chip Decoupling Capacitors.
IEEE Trans. VLSI Syst., 2008

On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits.
IEEE Trans. VLSI Syst., 2008

Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs.
IEEE Trans. VLSI Syst., 2008

Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis.
IEEE Trans. on Circuits and Systems, 2008

Timing-driven via placement heuristics for three-dimensional ICs.
Integr., 2008

Physical Design Issues in 3-D Integrated Technologies.
Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

Nanoscale on-chip decoupling capacitors.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

A higher-order mismatch-shaping method for multi-bit Sigma-Delta Modulators.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Pseudo-random clocking to enhance signal integrity.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Timing optimization in logic with interconnect.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Electrical modeling and characterization of 3-D vias.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Input port reduction for efficient substrate extraction in large scale IC's.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Equivalent rise time for resonance in power/ground noise estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Transient simulation of on-chip transmission lines via exact pole extraction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Clock distribution networks for 3-D ictegrated Circuits.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Design Methodology for Global Resonant H-Tree Clock Distribution Networks.
IEEE Trans. VLSI Syst., 2007

3-D Topologies for Networks-on-Chip.
IEEE Trans. VLSI Syst., 2007

Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Wire shaping of RLC interconnects.
Integr., 2007

Predictions of CMOS compatible on-chip optical interconnect.
Integr., 2007

On-chip optical interconnect for reduced delay uncertainty.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Substrate Noise Reduction Based On Noise Aware Cell Design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Quasi-Resonant Interconnects: A Low Power Design Methodology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Crosstalk modeling for coupled RLC interconnects with application to shield insertion.
IEEE Trans. VLSI Syst., 2006

Decoupling capacitors for multi-voltage power distribution systems.
IEEE Trans. VLSI Syst., 2006

Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints.
IEEE Trans. VLSI Syst., 2006

Sizing CMOS inverters with Miller Effect and Threshold voltage Variations.
Journal of Circuits, Systems, and Computers, 2006

Substrate and Ground Noise Interactions in Mixed-Signal Circuits.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

On-die decoupling capacitance: frequency domain analysis of activity radius.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Via placement for minimum interconnect delay in three-dimensional (3D) circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Optimum wire tapering for minimum power dissipation in RLC interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Effective capacitance of RLC loads for estimating short-circuit power.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Sensitivity evaluation of global resonant H-tree clock distribution networks.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Maximum effective distance of on-chip decoupling capacitors in power distribution grids.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005
Exponentially tapered H-tree clock distribution networks.
IEEE Trans. VLSI Syst., 2005

Shielding effect of on-chip interconnect inductance.
IEEE Trans. VLSI Syst., 2005

An RLC interconnect model based on fourier analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Monolithic voltage conversion in low-voltage CMOS technologies.
Microelectron. J., 2005

On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Noise coupling in multi-voltage power distribution systems with decoupling capacitors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Cascode buffer for monolithic voltage conversion operating at high input supply voltages.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Fourier series-based RLC interconnect model for periodic signals.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Low power repeaters driving RLC interconnects with delay and bandwidth constraints.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Electrical and optical on-chip interconnects in scaled microprocessors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Interconnect delay minimization through interlayer via placement in 3-D ICs.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004
Complex +/-1 Multiplier Based on Signed-Binary Transformations.
VLSI Signal Processing, 2004

Substrate coupling in digital circuits in mixed-signal smart-power systems.
IEEE Trans. VLSI Syst., 2004

Impedance characteristics of power distribution grids in nanoscale integrated circuits.
IEEE Trans. VLSI Syst., 2004

Scaling trends of on-chip power distribution noise.
IEEE Trans. VLSI Syst., 2004

Sleep switch dual threshold Voltage domino logic with reduced standby leakage current.
IEEE Trans. VLSI Syst., 2004

Power characteristics of inductive interconnect.
IEEE Trans. VLSI Syst., 2004

Low-voltage-swing monolithic dc-dc conversion.
IEEE Trans. on Circuits and Systems, 2004

Optimum wire sizing of RLC interconnect with repeaters .
Integr., 2004

Mutual inductance modeling for multiple RLC interconnects with application to shield insertion.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Clock tree layout design for reduced delay uncertainty.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Decoupling capacitors for power distribution systems with multiple power supply voltages.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Low power repeaters driving RC interconnects with delay and bandwidth constraints.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Buffer Sizing for Crosstalk Induced Delay Uncertainty.
Proceedings of the Integrated Circuit and System Design, 2004

High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Effect of shield insertion on reducing crosstalk noise between coupled interconnects.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Decoupling technique and crosstalk analysis for coupled RLC interconnects.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A low power thyristor-based CMOS programmable delay element.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Forward body biased keeper for enhanced noise immunity in domino logic circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Design and simulation of Fractional-N PLL frequency synthesizers.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Low power flexible Rake receivers for WCDMA.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Buffer sizing for delay uncertainty induced by process variations.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

A high-speed CMOS op-amp design technique using negative Miller capacitance.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

A 250 MHz delta-sigma modulator for low cost ultrasound/sonar beamforming applications.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

A bulk-driven CMOS OTA with 68 dB DC gain.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Impedance characteristics of decoupling capacitors in multi-power distribution systems.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Challenges in ultra deep submicrometer high performance VLSI circuits.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003
Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor.
IEEE Trans. VLSI Syst., 2003

Domino logic with variable threshold voltage keeper.
IEEE Trans. VLSI Syst., 2003

On the Extraction of On-Chip Inductance.
Journal of Circuits, Systems, and Computers, 2003

Dynamically Tuning Processor Resources with Adaptive Processing.
IEEE Computer, 2003

Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Electrical characteristics of multi-layer power distribution grids.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Inductive interconnect width optimization for low power.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Optimum wire sizing of RLC interconnect with repeaters.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Orthogonal code generator for 3G wireless transceivers.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Reduced Delay Uncertainty in High Performance Clock Distribution Networks.
Proceedings of the 2003 Design, 2003

2002
Simultaneous switching noise in on-chip CMOS power distribution networks.
IEEE Trans. VLSI Syst., 2002

Inductive properties of high-performance power distribution grids.
IEEE Trans. VLSI Syst., 2002

Retiming and clock scheduling for digital circuit optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling.
Journal of Circuits, Systems, and Computers, 2002

Inductance Effects in RLC Trees.
Journal of Circuits, Systems, and Computers, 2002

Managing static leakage energy in microprocessor functional units.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

A substrate noise circuit for accurately testing mixed-signal ICs.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Inductance/area/resistance tradeoffs in high performance power distribution grids.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Properties of on-chip inductive current loops.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Low swing dual threshold voltage domino logic.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Efficient implementation of a complex ±1 multiplier.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001
Exploiting the on-chip inductance in high-speed clock distribution networks.
IEEE Trans. VLSI Syst., 2001

A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Estimation of transient voltage fluctuations in the CMOS-based power distribution networks.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits.
IEEE Trans. VLSI Syst., 2000

Equivalent Elmore delay for RLC trees.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections.
Integr., 2000

Transient analysis of a CMOS inverter driving resistive interconnect.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Delay and power expressions characterizing a CMOS inverter driving an RLC load.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Sensitivity of interconnect delay to on-chip inductance.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Noise estimation due to signal activity for capacitively coupled CMOS logic gates.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

Transparent repeaters.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1999
System Timing.
Proceedings of the VLSI Handbook., 1999

Figures of merit to characterize the importance of on-chip inductance.
IEEE Trans. VLSI Syst., 1999

Interconnect coupling noise in CMOS VLSI circuits.
Proceedings of the 1999 International Symposium on Physical Design, 1999

Peak noise prediction in loosely coupled interconnect [VLSI circuits].
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A universal CMOS voltage interface circuit.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A high precision CMOS current mirror/divider.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Signal waveform characterization in RLC trees.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Repeater insertion in RLC lines for minimum propagation delay.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Clock skew scheduling for improved reliability via quadratic programming.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Repeater insertion in tree structured inductive interconnect.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits.
Proceedings of the 1999 Design, 1999

Maximizing Performance by Retiming and Clock Skew Scheduling.
Proceedings of the 36th Conference on Design Automation, 1999

Equivalent Elmore Delay for RLC Trees.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Automated Synthesis of Skew-Based Clock Distribution Networks.
VLSI Design, 1998

Power dissipated by CMOS gates driving lossless transmission lines.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997
Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations.
VLSI Signal Processing, 1997

Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits.
VLSI Signal Processing, 1997

High Performance Clock Distribution Networks.
VLSI Signal Processing, 1997

Incorporating interconnect, register, and clock distribution delays into the retiming process.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

1996
Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew.
IEEE Trans. VLSI Syst., 1996

Optimal Clock Skew Scheduling Tolerant to Process Variations.
Proceedings of the 33st Conference on Design Automation, 1996

1995
A unified design methodology for CMOS tapered buffers.
IEEE Trans. VLSI Syst., 1995

Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Channel width tapering of serially connected MOSFET's with emphasis on power dissipation.
IEEE Trans. VLSI Syst., 1994

Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer Design.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Retiming with non-zero clock skew, variable register, and interconnect delay.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993
Integration of Clock Skew and Register Delays into a Retiming Algorithm.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Clock Distribution Design in VLSI Circuits. An Overview.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1991
Clock frequency and latency in synchronous digital systems.
IEEE Trans. Signal Processing, 1991


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