Andrew Kinane

According to our database1, Andrew Kinane authored at least 8 papers between 2004 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2007
Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse.
J. VLSI Signal Process., 2007

Energy-Efficient Acceleration of MPEG-4 Compression Tools.
EURASIP J. Embed. Syst., 2007

2006
An Efficient Hardware Architecture for a Neural Network Activation Function Generator.
Proceedings of the Advances in Neural Networks - ISNN 2006, Third International Symposium on Neural Networks, Chengdu, China, May 28, 2006

Towards an optimised VLSI design algorithm for the constant matrix multiplication problem.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Towards Hardware Acceleration of Neuroevolution for Multimedia Processing Applications on Mobile Devices.
Proceedings of the Neural Information Processing, 13th International Conference, 2006

Optimisation of Constant Matrix Multiplication Operation Hardware Using a Genetic Algorithm.
Proceedings of the Applications of Evolutionary Computing, 2006

2005
FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

2004
Energy-Efficient Hardware Architecture for Variable N-point 1D DCT.
Proceedings of the Integrated Circuit and System Design, 2004


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