Valentin Muresan

According to our database, Valentin Muresan authored at least 15 papers between 2000 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2016

Superior vision: Always on human-like vision for intelligent devices.

Valentin Muresan

Proceedings of the 11th IEEE International Symposium on Applied Computational Intelligence and Informatics, 2016

2011

Requirements of a real-time multiprocessor operating system for multimedia applications.

Valentin Stangaciu, Georgiana Macariu, Mihai V. Micea, Valentin Muresan, Brendan Barry

Proceedings of the 6th IEEE International Symposium on Applied Computational Intelligence and Informatics, 2011

2006

An Efficient Hardware Architecture for a Neural Network Activation Function Generator.

Daniel Larkin, Andrew Kinane, Valentin Muresan, Noel E. O'Connor

Proceedings of the Advances in Neural Networks - ISNN 2006, Third International Symposium on Neural Networks, Chengdu, China, May 28, 2006

A low complexity hardware architecture for motion estimation.

Daniel Larkin, Valentin Muresan, Noel E. O'Connor

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Towards an optimised VLSI design algorithm for the constant matrix multiplication problem.

Andrew Kinane, Valentin Muresan, Noel E. O'Connor

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Optimisation of Constant Matrix Multiplication Operation Hardware Using a Genetic Algorithm.

Andrew Kinane, Valentin Muresan, Noel E. O'Connor

Proceedings of the Applications of Evolutionary Computing, 2006

2005

FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator.

Andrew Kinane, Alan Casey, Valentin Muresan, Noel E. O'Connor

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

2004

Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints.

Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu

J. Electron. Test., 2004

Energy-Efficient Hardware Architecture for Variable N-point 1D DCT.

Andrew Kinane, Valentin Muresan, Noel E. O'Connor, Noel Murphy, Seán Marlow

Proceedings of the Integrated Circuit and System Design, 2004

2001

Mixed Classical Scheduling Algorithms and Tree Growing Technique in Block-Test Scheduling under Power Constraints.

Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu

Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001

2000

The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints.

Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Power-Constrained Block-Test List Scheduling.

Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu

Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000

A comparison of classical scheduling approaches in power-constrained block-test scheduling.

Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

The left edge algorithm in block test scheduling under power constraints.

Valentin Muresan, Xiaojun Wang, Mircea Vladutiu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling.

Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000