Andrzej Krasniewski

According to our database, Andrzej Krasniewski authored at least 39 papers between 1984 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

Rule Induction Based on Logic Synthesis Methods.

Grzegorz Borowik, Andrzej Krasniewski, Tadeusz Luba

Proceedings of the Progress in Systems Engineering, 2014

2012

Evaluation of susceptibility of FPGA-based circuits to fault injection attacks based on clock glitching.

Jakub Korczyc, Andrzej Krasniewski

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011

A Tool for Trading-Off On-Line Error Detection Efficiency with Implementation Cost for Sequential Logic Implemented in FPGAs.

Grzegorz Borowik, Andrzej Krasniewski

Proceedings of the 21st International Conference on Systems Engineering (ICSEng 2011), 2011

Trading-Off Error Detection Efficiency with Implementation Cost for Sequential Circuits Implemented with FPGAs.

Grzegorz Borowik, Andrzej Krasniewski

Proceedings of the Computer Aided Systems Theory - EUROCAST 2011, 2011

2008

Concurrent error detection for finite state machines implemented with embedded memory blocks of SRAM-based FPGAs.

Andrzej Krasniewski

Microprocess. Microsystems, 2008

Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs.

Andrzej Krasniewski

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs.

Andrzej Krasniewski

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007

Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAs.

Andrzej Krasniewski

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006

Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAs.

Andrzej Krasniewski

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005

A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory.

Andrzej Krasniewski

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

2004

Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory Blocks.

Andrzej Krasniewski

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory.

Andrzej Krasniewski

Proceedings of the Field Programmable Logic and Application, 2004

Concurrent Error Detection in Sequential Circuits Implemented Using Embedded Memory of LUT-Based FPGAs.

Andrzej Krasniewski

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003

Evaluation of delay fault testability of LUTs for the enhancement of application-dependent testing of FPGAs.

Andrzej Krasniewski

J. Syst. Archit., 2003

Evaluation of the Quality of Testing Path Delay Faults under Restricted Input Assumption.

Andrzej Krasniewski

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices.

Andrzej Krasniewski

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002

Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs.

Andrzej Krasniewski

Proceedings of the Field-Programmable Logic and Applications, 2002

On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs.

Andrzej Krasniewski

Proceedings of the Field-Programmable Logic and Applications, 2002

2001

Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing.

Andrzej Krasniewski

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA Testing.

Andrzej Krasniewski

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

2000

Self-Testing of FPGA Delay Faults in the System Environment.

Andrzej Krasniewski

Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs.

Andrzej Krasniewski

Proceedings of the Field-Programmable Logic and Applications, 2000

1999

Self-Testing of S-Compatible Test Units in User-Programmed FPGAs.

Pawel Tomaszewicz, Andrzej Krasniewski

Proceedings of the 25th EUROMICRO '99 Conference, 1999

Application-Dependent Testing of FPGA Delay Faults.

Andrzej Krasniewski

Proceedings of the 25th EUROMICRO '99 Conference, 1999

1996

Design of Dependable Hardware: What BIST is most Efficient?

Andrzej Krasniewski

Proceedings of the Dependable Computing, 1996

1994

Tests for path delay faults vs. tests for gate delay faults: how different they are.

Andrzej Krasniewski, Leszek B. Wronski

Proceedings of the Proceedings EURO-DAC'94, 1994

Coverage of Delay Faults: When 13% and 99% Mean the Same.

Andrzej Krasniewski, Leszek B. Wronski

Proceedings of the Dependable Computing, 1994

1992

Estimating testing effectiveness of the circular self-test path technique.

Slawomir Pilarski, Andrzej Krasniewski, Tiko Kameda

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

High Quality Testing of Embedded RAMs Using Circular Self-Test Path.

Andrzej Krasniewski, Slawomir Pilarski

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Design of Robust-Path-Delay-Fault-Testable Combinational Circuits by Boolean Space Expansion.

Xiaodong Xie, Alexander Albicki, Andrzej Krasniewski

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991

Can Redundancy Enhance Testability?

Andrzej Krasniewski

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Random Testability of Redundant Circuits.

Andrzej Krasniewski, Alexander Albicki

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Logic Synthesis for Efficient Pseudoexhaustive Testability.

Andrzej Krasniewski

Proceedings of the 28th Design Automation Conference, 1991

1990

Design for verification testability.

Andrzej Krasniewski

Proceedings of the European Design Automation Conference, 1990

1989

Circular self-test path: a low-cost BIST technique for VLSI circuits.

Andrzej Krasniewski, Slawomir Pilarski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1987

Circular Self-Test Path: A Low-Cost BIST Technique.

Andrzej Krasniewski, Slawomir Pilarski

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1985

Automatic Design of Exhaustively Self-Testing Chips with Bilbo Modules.

Andrzej Krasniewski, Alexander Albicki

Proceedings of the Proceedings International Test Conference 1985, 1985

Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications.

Andrzej Krasniewski, Alexander Albicki

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984

Fuzzy Automata as Adaptive Algorithms for Telephone Traffic Routing.

Andrzej Krasniewski

Proceedings of the IEEE International Conference on Communications: Links for the Future, 1984