Ang-Chih Hsieh

According to our database, Ang-Chih Hsieh authored at least 9 papers between 2006 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2013

Utilizing circuit structure for scan chain diagnosis.

Wei-Hen Lo, Ang-Chih Hsieh, Chien-Ming Lan, Min-Hsien Lin, TingTing Hwang

Proceedings of the 18th IEEE European Test Symposium, 2013

2012

Run-Time Reconfiguration of Expandable Cache for Embedded Systems.

Ang-Chih Hsieh, TingTing Hwang

IEEE Trans. Very Large Scale Integr. Syst., 2012

TSV Redundancy: Architecture and Design Issues in 3-D IC.

Ang-Chih Hsieh, TingTing Hwang

IEEE Trans. Very Large Scale Integr. Syst., 2012

2011

Memory Mapping and Task Scheduling Techniques for Computation Models of Image Processing on Many-Core Platforms.

Ang-Chih Hsieh, Yi-Ta Wu, Shau-Yin Tseng, TingTing Hwang

Proceedings of the International Conference on Parallel Processing, 2011

Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary Translation.

Ang-Chih Hsieh, Chun-Cheng Liu, TingTing Hwang

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

TSV redundancy: Architecture and design issues in 3D IC.

Ang-Chih Hsieh, TingTing Hwang, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Thermal-aware memory mapping in 3D designs.

Ang-Chih Hsieh, TingTing Hwang

Proceedings of the Design, Automation and Test in Europe, 2009

2007

A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current.

Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang

ACM Trans. Design Autom. Electr. Syst., 2007

2006

Instruction buffering for nested loops in low-power design.

Chi Ta Wu, Ang-Chih Hsieh, TingTing Hwang

IEEE Trans. Very Large Scale Integr. Syst., 2006