TingTing Hwang

According to our database1, TingTing Hwang authored at least 94 papers between 1989 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
A Novel Privacy-Preserving Deep Learning Scheme without Using Cryptography Component.
CoRR, 2019

Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Crosstalk-aware TSV-buffer Insertion in 3D IC.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2017
A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Architectural evaluations on TSV redundancy for reliability enhancement.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Communication driven remapping of processing element (PE) in fault-tolerant NoC-based MPSoCs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Architecture of Ring-Based Redundant TSV for Clustered Faults.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Thermal-aware dynamic page allocation policy by future access patterns for Hybrid Memory Cube (HMC).
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2014
Utilizing Circuit Structure for Scan Chain Diagnosis.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Clock-Tree Synthesis with Methodology of Reuse in 3D-IC.
ACM J. Emerg. Technol. Comput. Syst., 2014

Compaction-free compressed cache for high performance multi-core system.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Fault-tolerant TSV by using scan-chain test TSV.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Thermal-aware memory mapping in 3D designs.
ACM Trans. Embed. Comput. Syst., 2013

Thread-criticality aware dynamic cache reconfiguration in multi-core system.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Stacking signal TSV for thermal dissipation in global routing for 3D IC.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Run-Time Reconfiguration of Expandable Cache for Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2012

TSV Redundancy: Architecture and Design Issues in 3-D IC.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Physical-Location-Aware X-Bit Redistribution for Maximum IR-Drop Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Clock tree synthesis with methodology of re-use in 3D IC.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Memory Mapping and Task Scheduling Techniques for Computation Models of Image Processing on Many-Core Platforms.
Proceedings of the International Conference on Parallel Processing, 2011

A new architecture for power network in 3D IC.
Proceedings of the Design, Automation and Test in Europe, 2011

Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary Translation.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

A physical-location-aware fault redistribution for maximum IR-drop reduction.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Randomness Enhancement Using Digitalized Modified Logistic Map.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A Fast Digital Chaotic Generator for Secure Communication.
Int. J. Bifurc. Chaos, 2010

TSV redundancy: Architecture and design issues in 3D IC.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Skew-aware polarity assignment in clock tree.
ACM Trans. Design Autom. Electr. Syst., 2009

Leakage reduction, delay compensation using partition-based tunable body-biasing techniques.
ACM Trans. Design Autom. Electr. Syst., 2009

A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test.
Proceedings of the Design, Automation and Test in Europe, 2009

New spare cell design for IR drop minimization in Engineering Change Order.
Proceedings of the 46th Design Automation Conference, 2009

Thermal-aware post compilation for VLIW architectures.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Synthesis of a novel timing-error detection architecture.
ACM Trans. Design Autom. Electr. Syst., 2008

Digital Secure-Communication Using Robust Hyper-Chaotic Systems.
Int. J. Bifurc. Chaos, 2008

Transition-aware decoupling-capacitor allocation in power noise reduction.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007
A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current.
ACM Trans. Design Autom. Electr. Syst., 2007

Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains.
J. Supercomput., 2007

Crosstalk-Aware Domino-Logic Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006
Instruction buffering for nested loops in low-power design.
IEEE Trans. Very Large Scale Integr. Syst., 2006

A power-driven multiplication instruction-set design method for ASIPs.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Crosstalk minimization in logic synthesis for PLAs.
ACM Trans. Design Autom. Electr. Syst., 2006

Decomposition of instruction decoders for low-power designs.
ACM Trans. Design Autom. Electr. Syst., 2006

Performance-driven crosstalk elimination at post-compiler level.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A bus architecture for crosstalk elimination in high performance processor design.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Switching-activity driven gate sizing and Vth assignment for low power design.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Low-power techniques for network security processors.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Functionality directed clustering for low power MTCMOS design.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Power-Aware Scheduling for Parallel Security Processors with Analytical Models.
Proceedings of the Languages and Compilers for High Performance Computing, 2004

Output-pattern directed decomposition for low power design.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Crosstalk Minimization in Logic Synthesis for PLA.
Proceedings of the 2004 Design, 2004

Decomposition of Instruction Decoder for Low Power Design.
Proceedings of the 2004 Design, 2004

Low power design using dual threshold voltage.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Compiler optimization on VLIW instruction scheduling for low power.
ACM Trans. Design Autom. Electr. Syst., 2003

A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs.
Proceedings of the 2003 Design, 2003

Decomposition of Extended Finite State Machine for Low Power Design.
Proceedings of the 2003 Design, 2003

G-MAC: An Application-Specific MAC/Co-Processor Synthesizer.
Proceedings of the 2003 Design, 2003

2002
Logic transformation for low-power synthesis.
ACM Trans. Design Autom. Electr. Syst., 2002

Instruction buffering for nested loops in low power design.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A technology mapping algorithm for CPLD architectures.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

2001
Architecture driven circuit partitioning.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Binary decision diagram with minimum expected path length.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

A construction of minimal delay Steiner tree using two-pole delay model.
Proceedings of ASP-DAC 2001, 2001

2000
Compiler Optimization on Instruction Scheduling for Low Power.
Proceedings of the 13th International Symposium on System Synthesis, 2000

1999
On determining sensitization criterion in an iterative gate sizing process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Logic Transformation for Low Power Synthesis.
Proceedings of the 1999 Design, 1999

A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
Layout Driven Selection and Chaining of Partial Scan Flip-Flops.
J. Electron. Test., 1998

A Re-engineering Approach to Low Power FPGA Design Using SPFD.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Boolean matching for incompletely specified functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Low Power FPGA Design - A Re-engineering Approach.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Low power realization of finite state machines - a decomposition approach.
ACM Trans. Design Autom. Electr. Syst., 1996

Exploiting communication complexity for Boolean matching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Layout Driven Selecting and Chaining of Partial Scan.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Combining technology mapping and placement for delay-minimization in FPGA designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Power recduction by gate sizing with path-oriented slack calculation.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Performance-driven interconnection optimization for microarchitecture synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Logic synthesis for field-programmable gate arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

State Assignment for Power and Area Minimization.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Dynamical identification of critical paths for iterative gate sizing.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Cell Height Driven Transistor Sizing in a Cell Based Module Design.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Combining technology mapping and placement for delay-optimization in FPGA designs.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
Efficiently computing communication complexity for multilevel logic synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

ELM-A Fast Addition Algorithm Discovered by a Program.
IEEE Trans. Computers, 1992

Performance-driven interconnection optimization for microarchitecture synthesis.
Proceedings of the conference on European design automation, 1992

1990
Exploiting communication complexity for multilevel logic synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Logic synthesis for programmable logic devices.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1989
Multi-Level Logic Synthesis Using Communication Complexity.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989


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