Chun-Cheng Liu

Orcid: 0000-0002-2337-5353

According to our database1, Chun-Cheng Liu authored at least 24 papers between 2009 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2021
Enhanced Over-Representation Analysis for the Differential Regulation of Birc5a and HIF2α-Knockdown Approaches.
J. Comput. Biol., 2021

2020
6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Enhanced Functional Pathway Annotations for Differentially Expressed Gene Clusters.
Proceedings of the Bioinformatics Research and Applications - 16th International Symposium, 2020

2019
A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2017
28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC.
IEEE J. Solid State Circuits, 2016

27.4 A 0.35mW 12b 100MS/s SAR-assisted digital slope ADC in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Biological Pathway Analysis for De Novo Transcriptomes through Multiple Reference Species Selections.
Proceedings of the 10th International Conference on Complex, 2016

2015
A 0.022 mm<sup>2</sup> 98.5 dB SNDR Hybrid Audio ΔΣ Modulator With Digital ELD Compensation in 28 nm CMOS.
IEEE J. Solid State Circuits, 2015

A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS.
IEEE J. Solid State Circuits, 2015

Exclusive Genomic Pathway Analysis for Groupers Infected by Different Iridovirus.
Proceedings of the Ninth International Conference on Complex, 2015

2014
A 0.022mm<sup>2</sup> 98.5dB SNDR hybrid audio delta-sigma modulator with digital ELD compensation in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
10-bit 30-MS/s SAR ADC Using a Switchback Switching Method.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Optimal Sensor Placement for Stay Cable Damage Identification of Cable-Stayed Bridge under Uncertainty.
Int. J. Distributed Sens. Networks, 2013

2012
A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications.
IEEE J. Solid State Circuits, 2012

2011
A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

Enhanced Heterogeneous Code Cache management scheme for Dynamic Binary Translation.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure.
IEEE J. Solid State Circuits, 2010

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009


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